📄 div.rpt
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F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 8 0 8 0 8 0 1 0 0 0 0 0 0 0 0 0 0 0 0 41/0
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
D12 - - - -- INPUT G ^ 0 0 0 0 CLKI
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
E22 - - A -- OUTPUT 0 1 0 0 CLKO
C22 - - A -- OUTPUT 0 1 0 0 sel0
D21 - - A -- OUTPUT 0 1 0 0 sel1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 38 AND2 0 2 0 1 |lpm_add_sub:179|addcore:adder|:119
- 1 - A 38 AND2 0 4 0 4 |lpm_add_sub:179|addcore:adder|:127
- 7 - A 28 AND2 0 2 0 1 |lpm_add_sub:179|addcore:adder|:131
- 3 - A 36 AND2 0 4 0 2 |lpm_add_sub:179|addcore:adder|:139
- 5 - A 36 AND2 0 2 0 4 |lpm_add_sub:179|addcore:adder|:143
- 7 - A 36 AND2 0 3 0 1 |lpm_add_sub:179|addcore:adder|:151
- 8 - A 36 AND2 0 4 0 3 |lpm_add_sub:179|addcore:adder|:155
- 5 - A 34 AND2 0 3 0 3 |lpm_add_sub:179|addcore:adder|:163
- 2 - A 34 AND2 0 3 0 3 |lpm_add_sub:179|addcore:adder|:171
- 3 - A 30 AND2 0 3 0 3 |lpm_add_sub:179|addcore:adder|:179
- 7 - A 30 AND2 0 2 0 1 |lpm_add_sub:179|addcore:adder|:183
- 3 - A 34 OR2 s 0 3 0 1 ~5~1
- 4 - A 34 OR2 s 0 3 0 1 ~5~2
- 2 - A 30 OR2 s 0 4 0 1 ~5~3
- 1 - A 34 OR2 s 0 4 0 2 ~5~4
- 4 - A 28 OR2 s 0 4 0 1 ~5~5
- 2 - A 38 OR2 s 0 4 0 1 ~5~6
- 5 - A 38 OR2 ! 0 4 0 20 :5
- 8 - A 30 DFFE + 0 3 0 1 Q19 (:72)
- 6 - A 30 DFFE + 0 3 0 2 Q18 (:73)
- 4 - A 30 DFFE + 0 2 0 3 Q17 (:74)
- 1 - A 30 DFFE + 0 3 0 2 Q16 (:75)
- 5 - A 30 DFFE + 0 2 0 3 Q15 (:76)
- 7 - A 34 DFFE + 0 3 0 2 Q14 (:77)
- 6 - A 34 DFFE + 0 2 0 3 Q13 (:78)
- 8 - A 34 DFFE + 0 3 0 2 Q12 (:79)
- 3 - A 28 DFFE + 0 2 0 3 Q11 (:80)
- 6 - A 36 DFFE + 0 2 0 2 Q10 (:81)
- 2 - A 36 DFFE + 0 3 1 3 Q9 (:82)
- 1 - A 36 DFFE + 0 2 1 5 Q8 (:83)
- 4 - A 36 DFFE + 0 2 0 3 Q7 (:84)
- 8 - A 28 DFFE + 0 3 0 3 Q6 (:85)
- 6 - A 28 DFFE + 0 3 0 4 Q5 (:86)
- 2 - A 28 DFFE + 0 2 0 5 Q4 (:87)
- 4 - A 38 DFFE + 0 3 0 3 Q3 (:88)
- 7 - A 38 DFFE + 0 3 0 4 Q2 (:89)
- 1 - A 28 DFFE + 0 2 0 5 Q1 (:90)
- 1 - A 40 DFFE + 0 1 0 6 Q0 (:91)
- 5 - A 28 AND2 s 0 4 0 1 ~172~1
- 8 - A 38 AND2 s 0 4 0 1 ~172~2
- 6 - A 38 OR2 0 4 1 0 :172
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/208( 7%) 0/104( 0%) 8/104( 7%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 CLKI
Device-Specific Information: c:\maxplus2\verilog6\div.rpt
div
** EQUATIONS **
CLKI : INPUT;
-- Node name is 'CLKO'
-- Equation name is 'CLKO', type is output
CLKO = _LC6_A38;
-- Node name is ':91' = 'Q0'
-- Equation name is 'Q0', location is LC1_A40, type is buried.
Q0 = DFFE( _EQ001, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ001 = !_LC5_A38 & !Q0;
-- Node name is ':90' = 'Q1'
-- Equation name is 'Q1', location is LC1_A28, type is buried.
Q1 = DFFE( _EQ002, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ002 = !_LC5_A38 & Q0 & !Q1
# !_LC5_A38 & !Q0 & Q1;
-- Node name is ':89' = 'Q2'
-- Equation name is 'Q2', location is LC7_A38, type is buried.
Q2 = DFFE( _EQ003, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ003 = !_LC5_A38 & !Q0 & Q2
# !_LC5_A38 & !Q1 & Q2
# !_LC5_A38 & Q0 & Q1 & !Q2;
-- Node name is ':88' = 'Q3'
-- Equation name is 'Q3', location is LC4_A38, type is buried.
Q3 = DFFE( _EQ004, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ004 = !_LC5_A38 & !Q2 & Q3
# !_LC3_A38 & !_LC5_A38 & Q3
# _LC3_A38 & !_LC5_A38 & Q2 & !Q3;
-- Node name is ':87' = 'Q4'
-- Equation name is 'Q4', location is LC2_A28, type is buried.
Q4 = DFFE( _EQ005, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ005 = !_LC1_A38 & !_LC5_A38 & Q4
# _LC1_A38 & !_LC5_A38 & !Q4;
-- Node name is ':86' = 'Q5'
-- Equation name is 'Q5', location is LC6_A28, type is buried.
Q5 = DFFE( _EQ006, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ006 = !_LC5_A38 & !Q4 & Q5
# !_LC1_A38 & !_LC5_A38 & Q5
# _LC1_A38 & !_LC5_A38 & Q4 & !Q5;
-- Node name is ':85' = 'Q6'
-- Equation name is 'Q6', location is LC8_A28, type is buried.
Q6 = DFFE( _EQ007, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ007 = !_LC5_A38 & !Q5 & Q6
# !_LC5_A38 & !_LC7_A28 & Q6
# !_LC5_A38 & _LC7_A28 & Q5 & !Q6;
-- Node name is ':84' = 'Q7'
-- Equation name is 'Q7', location is LC4_A36, type is buried.
Q7 = DFFE( _EQ008, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ008 = !_LC3_A36 & !_LC5_A38 & Q7
# _LC3_A36 & !_LC5_A38 & !Q7;
-- Node name is ':83' = 'Q8'
-- Equation name is 'Q8', location is LC1_A36, type is buried.
Q8 = DFFE( _EQ009, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ009 = !_LC5_A36 & !_LC5_A38 & Q8
# _LC5_A36 & !_LC5_A38 & !Q8;
-- Node name is ':82' = 'Q9'
-- Equation name is 'Q9', location is LC2_A36, type is buried.
Q9 = DFFE( _EQ010, GLOBAL( CLKI), VCC, VCC, VCC);
_EQ010 = !_LC5_A38 & !Q8 & Q9
# !_LC5_A36 & !_LC5_A38 & Q9
# _LC5_A36 & !_LC5_A38 & Q8 & !Q9;
-- Node name is ':81' = 'Q10'
-- Equation name is 'Q10', location is LC6_A36, type is buried.
Q10 = DFFE( _EQ011, GLOBAL( CLKI), VCC, VCC, VCC);
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