btoseven.v

来自「verilog除頻器可用於編碼段運用可以穩定電路設計」· Verilog 代码 · 共 23 行

module btoseven(bin,p,sout);
input [3:0] bin;
input p;
output [7:0] sout;
reg [7:0] sout;
always@(bin)
begin
case(bin)
4'h0:sout={p,(7'b0111111)};
4'h1:sout={p,(7'b0000110)};
4'h2:sout={p,(7'b1011011)};
4'h3:sout={p,(7'b1001111)};
4'h4:sout={p,(7'b1100110)};
4'h5:sout={p,(7'b1101101)};
4'h6:sout={p,(7'b1111101)};
4'h7:sout={p,(7'b0000111)};
4'h8:sout={p,(7'b1111111)};
4'h9:sout={p,(7'b1101111)};
default:sout=(8'b00000000);
endcase
end
endmodule