cnts.v

来自「verilog除頻器可用於編碼段運用可以穩定電路設計」· Verilog 代码 · 共 22 行

module cnts(mclk,en,cq,s10s);
input mclk,en;
output [3:0] cq;
output s10s;
reg s10s;
reg [3:0] cq;
always@(negedge mclk)
begin
if(en&!(cq==9))
   cq<=cq+1;
else if(en&(cq==9))
   cq<=0;
end
always@(negedge mclk)
begin
if(cq==9)
   s10s=1;
else
   s10s=0;
end
endmodule