cns2.v

来自「verilog除頻器可用於編碼段運用可以穩定電路設計」· Verilog 代码 · 共 22 行

module cns2(clk,cq,m1s);
input clk;
output [3:0] cq;
output m1s;
reg m1s;
reg [3:0] cq;
always@(posedge clk)
begin
if(!(cq==5))
   cq<=cq+1;
else if((cq==5))
   cq<=0;
end
always@(posedge clk)
begin
if(cq==5)
   m1s=1;
else
   m1s=0;
end
endmodule