for4bitmux4.rpt

verilog除頻器可用於編碼段運用可以穩定電路設計

b3       : INPUT;
c0       : INPUT;
c1       : INPUT;
c2       : INPUT;
c3       : INPUT;
d0       : INPUT;
d1       : INPUT;
d2       : INPUT;
d3       : INPUT;
sel0     : INPUT;
sel1     : INPUT;

-- Node name is 'ds0' 
-- Equation name is 'ds0', type is output 
ds0      =  _LC5_H46;

-- Node name is 'ds1' 
-- Equation name is 'ds1', type is output 
ds1      =  _LC1_B44;

-- Node name is 'ds2' 
-- Equation name is 'ds2', type is output 
ds2      =  _LC6_H46;

-- Node name is 'ds3' 
-- Equation name is 'ds3', type is output 
ds3      = !_LC8_A7;

-- Node name is 'p' 
-- Equation name is 'p', type is output 
p        =  _LC6_B44;

-- Node name is 'y0' 
-- Equation name is 'y0', type is output 
y0       =  _LC8_H46;

-- Node name is 'y1' 
-- Equation name is 'y1', type is output 
y1       =  _LC2_H46;

-- Node name is 'y2' 
-- Equation name is 'y2', type is output 
y2       =  _LC4_B44;

-- Node name is 'y3' 
-- Equation name is 'y3', type is output 
y3       =  _LC2_B44;

-- Node name is ':28' 
-- Equation name is '_LC5_H46', type is buried 
_LC5_H46 = LCELL( _EQ001);
  _EQ001 = !sel0 & !sel1;

-- Node name is ':35' 
-- Equation name is '_LC1_B44', type is buried 
_LC1_B44 = LCELL( _EQ002);
  _EQ002 =  sel0 & !sel1;

-- Node name is '~42~1' 
-- Equation name is '~42~1', location is LC6_H46, type is buried.
-- synthesized logic cell 
_LC6_H46 = LCELL( _EQ003);
  _EQ003 = !sel0 &  sel1;

-- Node name is ':42' 
-- Equation name is '_LC6_B44', type is buried 
_LC6_B44 = LCELL( _EQ004);
  _EQ004 = !sel0 &  sel1;

-- Node name is ':50' 
-- Equation name is '_LC8_A7', type is buried 
!_LC8_A7 = _LC8_A7~NOT;
_LC8_A7~NOT = LCELL( _EQ005);
  _EQ005 =  sel0 &  sel1;

-- Node name is '~56~1' 
-- Equation name is '~56~1', location is LC7_B44, type is buried.
-- synthesized logic cell 
_LC7_B44 = LCELL( _EQ006);
  _EQ006 =  c3 &  _LC1_B44
         #  b3 &  _LC6_B44;

-- Node name is '~56~2' 
-- Equation name is '~56~2', location is LC8_B44, type is buried.
-- synthesized logic cell 
_LC8_B44 = LCELL( _EQ007);
  _EQ007 =  _LC7_B44
         #  d3 & !sel0 & !sel1;

-- Node name is ':56' 
-- Equation name is '_LC2_B44', type is buried 
_LC2_B44 = LCELL( _EQ008);
  _EQ008 =  a3 &  sel0 &  sel1
         #  _LC8_B44;

-- Node name is '~57~1' 
-- Equation name is '~57~1', location is LC3_B44, type is buried.
-- synthesized logic cell 
_LC3_B44 = LCELL( _EQ009);
  _EQ009 =  c2 &  _LC1_B44
         #  b2 &  _LC6_B44;

-- Node name is '~57~2' 
-- Equation name is '~57~2', location is LC5_B44, type is buried.
-- synthesized logic cell 
_LC5_B44 = LCELL( _EQ010);
  _EQ010 =  _LC3_B44
         #  d2 & !sel0 & !sel1;

-- Node name is ':57' 
-- Equation name is '_LC4_B44', type is buried 
_LC4_B44 = LCELL( _EQ011);
  _EQ011 =  a2 &  sel0 &  sel1
         #  _LC5_B44;

-- Node name is '~58~1' 
-- Equation name is '~58~1', location is LC4_H46, type is buried.
-- synthesized logic cell 
_LC4_H46 = LCELL( _EQ012);
  _EQ012 =  c1 &  _LC1_B44
         #  b1 &  _LC6_B44;

-- Node name is '~58~2' 
-- Equation name is '~58~2', location is LC7_H46, type is buried.
-- synthesized logic cell 
_LC7_H46 = LCELL( _EQ013);
  _EQ013 =  _LC4_H46
         #  d1 & !sel0 & !sel1;

-- Node name is ':58' 
-- Equation name is '_LC2_H46', type is buried 
_LC2_H46 = LCELL( _EQ014);
  _EQ014 =  a1 &  sel0 &  sel1
         #  _LC7_H46;

-- Node name is '~59~1' 
-- Equation name is '~59~1', location is LC1_H46, type is buried.
-- synthesized logic cell 
_LC1_H46 = LCELL( _EQ015);
  _EQ015 =  c0 &  _LC1_B44
         #  b0 &  _LC6_B44;

-- Node name is '~59~2' 
-- Equation name is '~59~2', location is LC3_H46, type is buried.
-- synthesized logic cell 
_LC3_H46 = LCELL( _EQ016);
  _EQ016 =  _LC1_H46
         #  d0 & !sel0 & !sel1;

-- Node name is ':59' 
-- Equation name is '_LC8_H46', type is buried 
_LC8_H46 = LCELL( _EQ017);
  _EQ017 =  a0 &  sel0 &  sel1
         #  _LC3_H46;



Project Information                       c:\maxplus2\verilog6\for4bitmux4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:10
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:13


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,000K