📄 cns2.rpt
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Device-Specific Information: c:\maxplus2\verilog6\cns2.rpt
cns2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: c:\maxplus2\verilog6\cns2.rpt
cns2
** EQUATIONS **
clk : INPUT;
-- Node name is 'cq0'
-- Equation name is 'cq0', type is output
cq0 = _LC8_F3;
-- Node name is 'cq1'
-- Equation name is 'cq1', type is output
cq1 = _LC1_F3;
-- Node name is 'cq2'
-- Equation name is 'cq2', type is output
cq2 = _LC2_F3;
-- Node name is 'cq3'
-- Equation name is 'cq3', type is output
cq3 = _LC7_F3;
-- Node name is 'm1s'
-- Equation name is 'm1s', type is output
m1s = _LC3_F3;
-- Node name is ':42'
-- Equation name is '_LC7_F3', type is buried
_LC7_F3 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC1_F3 & _LC7_F3
# _LC7_F3 & !_LC8_F3
# !_LC2_F3 & _LC7_F3
# _LC1_F3 & _LC2_F3 & !_LC7_F3 & _LC8_F3;
-- Node name is ':43'
-- Equation name is '_LC2_F3', type is buried
_LC2_F3 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC2_F3 & !_LC8_F3
# _LC1_F3 & !_LC2_F3 & _LC8_F3
# !_LC1_F3 & _LC2_F3 & _LC7_F3;
-- Node name is ':44'
-- Equation name is '_LC1_F3', type is buried
_LC1_F3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC1_F3 & !_LC8_F3
# !_LC1_F3 & _LC7_F3 & _LC8_F3
# !_LC1_F3 & !_LC2_F3 & _LC8_F3;
-- Node name is ':45'
-- Equation name is '_LC8_F3', type is buried
_LC8_F3 = DFFE(!_LC8_F3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':55'
-- Equation name is '_LC3_F3', type is buried
_LC3_F3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_F3 & _LC2_F3 & !_LC7_F3 & _LC8_F3;
Project Information c:\maxplus2\verilog6\cns2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:09
Timing SNF Extractor 00:00:01
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:14
Memory Allocated
-----------------
Peak memory allocated during compilation = 52,168K
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