normal.rpt

verilog除頻器可用於編碼段運用可以穩定電路設計

-- Node name is '|div:5|~5~1' 
-- Equation name is '_LC2_I37', type is buried 
-- synthesized logic cell 
_LC2_I37 = LCELL( _EQ061);
  _EQ061 =  _LC1_I37
         #  _LC4_I37
         # !_LC5_I37
         # !_LC7_I37;

-- Node name is '|div:5|~5~2' 
-- Equation name is '_LC1_I45', type is buried 
-- synthesized logic cell 
_LC1_I45 = LCELL( _EQ062);
  _EQ062 = !_LC5_I45
         # !_LC6_I45
         #  _LC7_I45
         #  _LC8_I37;

-- Node name is '|div:5|~5~3' 
-- Equation name is '_LC4_I45', type is buried 
-- synthesized logic cell 
_LC4_I45 = LCELL( _EQ063);
  _EQ063 =  _LC2_I37
         #  _LC1_I45
         # !_LC4_I19
         #  _LC8_I45;

-- Node name is '|div:5|~5~4' 
-- Equation name is '_LC3_K30', type is buried 
-- synthesized logic cell 
_LC3_K30 = LCELL( _EQ064);
  _EQ064 =  _LC4_K49
         #  _LC8_K30
         #  _LC3_K41
         #  _LC8_K41;

-- Node name is '|div:5|~5~5' 
-- Equation name is '_LC5_K30', type is buried 
-- synthesized logic cell 
_LC5_K30 = LCELL( _EQ065);
  _EQ065 =  _LC3_K49
         #  _LC2_K41
         #  _LC2_K49
         #  _LC6_K41;

-- Node name is '|div:5|:5' 
-- Equation name is '_LC4_K30', type is buried 
!_LC4_K30 = _LC4_K30~NOT;
_LC4_K30~NOT = LCELL( _EQ066);
  _EQ066 =  _LC4_I45
         #  _LC3_K30
         #  _LC5_K30
         # !_LC2_K19;

-- Node name is '|div:5|~172~1' 
-- Equation name is '_LC5_K41', type is buried 
-- synthesized logic cell 
_LC5_K41 = LCELL( _EQ067);
  _EQ067 = !_LC3_K41 & !_LC8_K41;

-- Node name is '|div:5|~172~2' 
-- Equation name is '_LC7_K30', type is buried 
-- synthesized logic cell 
_LC7_K30 = LCELL( _EQ068);
  _EQ068 = !_LC4_K49
         # !_LC8_K30
         # !_LC6_K41;

-- Node name is '|div:5|~172~3' 
-- Equation name is '_LC1_K30', type is buried 
-- synthesized logic cell 
_LC1_K30 = LCELL( _EQ069);
  _EQ069 = !_LC2_K49
         #  _LC7_K30
         # !_LC3_K49
         # !_LC2_K41;

-- Node name is '|div:5|:172' 
-- Equation name is '_LC4_K41', type is buried 
!_LC4_K41 = _LC4_K41~NOT;
_LC4_K41~NOT = LCELL( _EQ070);
  _EQ070 =  _LC5_K41
         #  _LC1_K30
         # !_LC8_I19
         #  _LC4_I45;

-- Node name is '|for4bitmux4:7|:28' 
-- Equation name is '_LC8_I19', type is buried 
!_LC8_I19 = _LC8_I19~NOT;
_LC8_I19~NOT = LCELL( _EQ071);
  _EQ071 =  _LC3_I19
         #  _LC1_I19;

-- Node name is '|for4bitmux4:7|:35' 
-- Equation name is '_LC2_K19', type is buried 
!_LC2_K19 = _LC2_K19~NOT;
_LC2_K19~NOT = LCELL( _EQ072);
  _EQ072 =  _LC3_I19
         # !_LC1_I19;

-- Node name is '|for4bitmux4:7|:42' 
-- Equation name is '_LC1_K20', type is buried 
_LC1_K20 = LCELL( _EQ073);
  _EQ073 = !_LC1_I19 &  _LC3_I19;

-- Node name is '|for4bitmux4:7|:50' 
-- Equation name is '_LC3_K18', type is buried 
!_LC3_K18 = _LC3_K18~NOT;
_LC3_K18~NOT = LCELL( _EQ074);
  _EQ074 =  _LC1_I19 &  _LC3_I19;

-- Node name is '|for4bitmux4:7|~56~1' 
-- Equation name is '_LC1_K3', type is buried 
-- synthesized logic cell 
!_LC1_K3 = _LC1_K3~NOT;
_LC1_K3~NOT = LCELL( _EQ075);
  _EQ075 =  _LC2_K1 &  _LC2_K19
         #  _LC7_K3 &  _LC8_I19;

-- Node name is '|for4bitmux4:7|~56~2' 
-- Equation name is '_LC3_K2', type is buried 
-- synthesized logic cell 
!_LC3_K2 = _LC3_K2~NOT;
_LC3_K2~NOT = LCELL( _EQ076);
  _EQ076 = !_LC1_I19 &  _LC3_I19 &  _LC6_K2
         # !_LC1_K3;

-- Node name is '|for4bitmux4:7|:56' 
-- Equation name is '_LC3_K14', type is buried 
_LC3_K14 = LCELL( _EQ077);
  _EQ077 =  _LC1_I19 &  _LC3_I19 &  _LC5_K19
         # !_LC3_K2;

-- Node name is '|for4bitmux4:7|~57~1' 
-- Equation name is '_LC4_K1', type is buried 
-- synthesized logic cell 
!_LC4_K1 = _LC4_K1~NOT;
_LC4_K1~NOT = LCELL( _EQ078);
  _EQ078 = !_LC3_K3 & !_LC6_K1
         # !_LC2_K19 & !_LC3_K3
         # !_LC6_K1 & !_LC8_I19
         # !_LC2_K19 & !_LC8_I19;

-- Node name is '|for4bitmux4:7|~57~2' 
-- Equation name is '_LC2_K2', type is buried 
-- synthesized logic cell 
!_LC2_K2 = _LC2_K2~NOT;
_LC2_K2~NOT = LCELL( _EQ079);
  _EQ079 = !_LC3_I19 & !_LC4_K1
         #  _LC1_I19 & !_LC4_K1
         # !_LC4_K1 & !_LC7_K2;

-- Node name is '|for4bitmux4:7|:57' 
-- Equation name is '_LC5_K14', type is buried 
!_LC5_K14 = _LC5_K14~NOT;
_LC5_K14~NOT = LCELL( _EQ080);
  _EQ080 = !_LC2_K2 & !_LC3_I19
         # !_LC1_I19 & !_LC2_K2
         # !_LC2_K2 & !_LC4_K19;

-- Node name is '|for4bitmux4:7|~58~1' 
-- Equation name is '_LC5_K1', type is buried 
-- synthesized logic cell 
_LC5_K1  = LCELL( _EQ081);
  _EQ081 = !_LC2_K3 & !_LC7_K1
         # !_LC2_K3 & !_LC2_K19
         # !_LC7_K1 & !_LC8_I19
         # !_LC2_K19 & !_LC8_I19;

-- Node name is '|for4bitmux4:7|~58~2' 
-- Equation name is '_LC1_K2', type is buried 
-- synthesized logic cell 
_LC1_K2  = LCELL( _EQ082);
  _EQ082 = !_LC3_I19 &  _LC5_K1
         #  _LC1_I19 &  _LC5_K1
         #  _LC5_K1 & !_LC8_K2;

-- Node name is '|for4bitmux4:7|:58' 
-- Equation name is '_LC2_K18', type is buried 
!_LC2_K18 = _LC2_K18~NOT;
_LC2_K18~NOT = LCELL( _EQ083);
  _EQ083 =  _LC1_K2 & !_LC3_I19
         # !_LC1_I19 &  _LC1_K2
         #  _LC1_K2 & !_LC3_K19;

-- Node name is '|for4bitmux4:7|~59~1' 
-- Equation name is '_LC7_K19', type is buried 
-- synthesized logic cell 
!_LC7_K19 = _LC7_K19~NOT;
_LC7_K19~NOT = LCELL( _EQ084);
  _EQ084 =  _LC1_K1 &  _LC2_K19
         #  _LC1_K41 &  _LC8_I19;

-- Node name is '|for4bitmux4:7|~59~2' 
-- Equation name is '_LC8_K19', type is buried 
-- synthesized logic cell 
!_LC8_K19 = _LC8_K19~NOT;
_LC8_K19~NOT = LCELL( _EQ085);
  _EQ085 = !_LC1_I19 &  _LC3_I19 &  _LC4_K2
         # !_LC7_K19;

-- Node name is '|for4bitmux4:7|:59' 
-- Equation name is '_LC1_K19', type is buried 
_LC1_K19 = LCELL( _EQ086);
  _EQ086 =  _LC1_I19 &  _LC3_I19 &  _LC6_K19
         # !_LC8_K19;



Project Information                            c:\maxplus2\verilog6\normal.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter