📄 normal.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 7/208( 3%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 18/208( 8%) 24/104( 23%) 2/104( 1%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 1/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\verilog6\normal.rpt
normal
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
DFF 5 |cns2:1|:55
DFF 5 |cnts:3|:63
LCELL 5 |div:5|:172
DFF 4 |cntm:2|:58
Device-Specific Information: c:\maxplus2\verilog6\normal.rpt
normal
** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'ds0'
-- Equation name is 'ds0', type is output
ds0 = _LC8_I19;
-- Node name is 'ds1'
-- Equation name is 'ds1', type is output
ds1 = _LC2_K19;
-- Node name is 'ds2'
-- Equation name is 'ds2', type is output
ds2 = _LC1_K20;
-- Node name is 'ds3'
-- Equation name is 'ds3', type is output
ds3 = !_LC3_K18;
-- Node name is 'sout0'
-- Equation name is 'sout0', type is output
sout0 = _LC1_K18;
-- Node name is 'sout1'
-- Equation name is 'sout1', type is output
sout1 = _LC7_K14;
-- Node name is 'sout2'
-- Equation name is 'sout2', type is output
sout2 = _LC2_K16;
-- Node name is 'sout3'
-- Equation name is 'sout3', type is output
sout3 = _LC1_K15;
-- Node name is 'sout4'
-- Equation name is 'sout4', type is output
sout4 = _LC4_K14;
-- Node name is 'sout5'
-- Equation name is 'sout5', type is output
sout5 = _LC4_K18;
-- Node name is 'sout6'
-- Equation name is 'sout6', type is output
sout6 = _LC1_K9;
-- Node name is 'sout7'
-- Equation name is 'sout7', type is output
sout7 = _LC2_K14;
-- Node name is '|btoseven:6|:53'
-- Equation name is '_LC6_K14', type is buried
_LC6_K14 = LCELL( _EQ001);
_EQ001 = _LC1_K19 & _LC2_K18 & !_LC3_K14 & !_LC5_K14;
-- Node name is '|btoseven:6|~162~1'
-- Equation name is '_LC8_K14', type is buried
-- synthesized logic cell
_LC8_K14 = LCELL( _EQ002);
_EQ002 = !_LC1_K19 & _LC2_K18 & !_LC3_K14 & _LC5_K14
# _LC1_K19 & !_LC2_K18 & !_LC3_K14 & _LC5_K14;
-- Node name is '|btoseven:6|:162'
-- Equation name is '_LC2_K14', type is buried
_LC2_K14 = LCELL( _EQ003);
_EQ003 = !_LC1_I19 & _LC3_I19 & _LC8_K14
# !_LC1_I19 & _LC3_I19 & _LC7_K14;
-- Node name is '|btoseven:6|:163'
-- Equation name is '_LC1_K9', type is buried
_LC1_K9 = LCELL( _EQ004);
_EQ004 = !_LC2_K18 & !_LC3_K14 & _LC5_K14
# _LC2_K18 & !_LC3_K14 & !_LC5_K14
# !_LC1_K19 & !_LC3_K14 & _LC5_K14
# !_LC2_K18 & _LC3_K14 & !_LC5_K14;
-- Node name is '|btoseven:6|:164'
-- Equation name is '_LC4_K18', type is buried
_LC4_K18 = LCELL( _EQ005);
_EQ005 = !_LC1_K19 & !_LC3_K14 & _LC5_K14
# !_LC1_K19 & !_LC2_K18 & !_LC5_K14
# !_LC2_K18 & !_LC3_K14 & _LC5_K14
# !_LC2_K18 & _LC3_K14 & !_LC5_K14;
-- Node name is '|btoseven:6|:165'
-- Equation name is '_LC4_K14', type is buried
_LC4_K14 = LCELL( _EQ006);
_EQ006 = !_LC1_K19 & !_LC3_K14 & !_LC5_K14
# !_LC1_K19 & _LC2_K18 & !_LC3_K14
# !_LC1_K19 & !_LC2_K18 & !_LC5_K14;
-- Node name is '|btoseven:6|:166'
-- Equation name is '_LC1_K15', type is buried
_LC1_K15 = LCELL( _EQ007);
_EQ007 = !_LC1_K19 & !_LC3_K14 & !_LC5_K14
# !_LC1_K19 & _LC2_K18 & !_LC3_K14
# !_LC1_K19 & !_LC2_K18 & !_LC5_K14
# _LC1_K19 & !_LC2_K18 & !_LC3_K14 & _LC5_K14
# _LC2_K18 & !_LC3_K14 & !_LC5_K14
# !_LC2_K18 & _LC3_K14 & !_LC5_K14;
-- Node name is '|btoseven:6|:167'
-- Equation name is '_LC2_K16', type is buried
_LC2_K16 = LCELL( _EQ008);
_EQ008 = _LC4_K18
# _LC1_K14
# _LC6_K14;
-- Node name is '|btoseven:6|~168~1'
-- Equation name is '_LC1_K14', type is buried
-- synthesized logic cell
_LC1_K14 = LCELL( _EQ009);
_EQ009 = _LC1_K19 & !_LC2_K18 & !_LC3_K14 & !_LC5_K14
# _LC1_K19 & _LC2_K18 & !_LC3_K14 & _LC5_K14;
-- Node name is '|btoseven:6|:168'
-- Equation name is '_LC7_K14', type is buried
_LC7_K14 = LCELL( _EQ010);
_EQ010 = !_LC1_K19 & !_LC2_K18 & !_LC3_K14
# _LC1_K19 & _LC2_K18 & !_LC3_K14
# !_LC3_K14 & !_LC5_K14
# !_LC2_K18 & !_LC5_K14;
-- Node name is '|btoseven:6|:169'
-- Equation name is '_LC1_K18', type is buried
_LC1_K18 = LCELL( _EQ011);
_EQ011 = !_LC1_K19 & !_LC3_K14 & !_LC5_K14
# _LC2_K18 & !_LC3_K14 & _LC5_K14
# !_LC1_K19 & !_LC2_K18 & !_LC5_K14
# _LC1_K19 & !_LC3_K14 & _LC5_K14
# _LC1_K19 & _LC2_K18 & !_LC3_K14
# !_LC2_K18 & _LC3_K14 & !_LC5_K14;
-- Node name is '|cns2:1|:42'
-- Equation name is '_LC2_K1', type is buried
_LC2_K1 = DFFE( _EQ012, _LC4_K3, VCC, VCC, VCC);
_EQ012 = _LC2_K1 & !_LC6_K1
# !_LC1_K1 & _LC2_K1
# _LC2_K1 & !_LC7_K1
# _LC1_K1 & !_LC2_K1 & _LC6_K1 & _LC7_K1;
-- Node name is '|cns2:1|:43'
-- Equation name is '_LC6_K1', type is buried
_LC6_K1 = DFFE( _EQ013, _LC4_K3, VCC, VCC, VCC);
_EQ013 = !_LC1_K1 & _LC6_K1
# _LC1_K1 & !_LC6_K1 & _LC7_K1
# _LC2_K1 & _LC6_K1 & !_LC7_K1;
-- Node name is '|cns2:1|:44'
-- Equation name is '_LC7_K1', type is buried
_LC7_K1 = DFFE( _EQ014, _LC4_K3, VCC, VCC, VCC);
_EQ014 = !_LC1_K1 & _LC7_K1
# _LC1_K1 & !_LC6_K1 & !_LC7_K1
# _LC1_K1 & _LC2_K1 & !_LC7_K1;
-- Node name is '|cns2:1|:45'
-- Equation name is '_LC1_K1', type is buried
_LC1_K1 = DFFE(!_LC1_K1, _LC4_K3, VCC, VCC, VCC);
-- Node name is '|cns2:1|:55'
-- Equation name is '_LC3_K1', type is buried
_LC3_K1 = DFFE( _EQ015, _LC4_K3, VCC, VCC, VCC);
_EQ015 = _LC1_K1 & !_LC2_K1 & _LC6_K1 & !_LC7_K1;
-- Node name is '|cntm2:4|:41'
-- Equation name is '_LC5_K19', type is buried
_LC5_K19 = DFFE( _EQ016, _LC5_K2, VCC, VCC, VCC);
_EQ016 = !_LC4_K19 & _LC5_K19
# _LC5_K19 & !_LC6_K19
# !_LC3_K19 & _LC5_K19
# _LC3_K19 & _LC4_K19 & !_LC5_K19 & _LC6_K19;
-- Node name is '|cntm2:4|:42'
-- Equation name is '_LC4_K19', type is buried
_LC4_K19 = DFFE( _EQ017, _LC5_K2, VCC, VCC, VCC);
_EQ017 = _LC4_K19 & !_LC6_K19
# _LC3_K19 & !_LC4_K19 & _LC6_K19
# !_LC3_K19 & _LC4_K19 & _LC5_K19;
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