btoseven.rpt

verilog除頻器可用於編碼段運用可以穩定電路設計

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Device-Specific Information:                 c:\maxplus2\verilog6\btoseven.rpt
btoseven

** EQUATIONS **

bin0     : INPUT;
bin1     : INPUT;
bin2     : INPUT;
bin3     : INPUT;
p        : INPUT;

-- Node name is 'sout0' 
-- Equation name is 'sout0', type is output 
sout0    =  _LC3_K43;

-- Node name is 'sout1' 
-- Equation name is 'sout1', type is output 
sout1    =  _LC1_K43;

-- Node name is 'sout2' 
-- Equation name is 'sout2', type is output 
sout2    =  _LC4_K43;

-- Node name is 'sout3' 
-- Equation name is 'sout3', type is output 
sout3    =  _LC6_D4;

-- Node name is 'sout4' 
-- Equation name is 'sout4', type is output 
sout4    =  _LC2_D4;

-- Node name is 'sout5' 
-- Equation name is 'sout5', type is output 
sout5    =  _LC6_K43;

-- Node name is 'sout6' 
-- Equation name is 'sout6', type is output 
sout6    =  _LC8_D4;

-- Node name is 'sout7' 
-- Equation name is 'sout7', type is output 
sout7    =  _LC5_K43;

-- Node name is ':53' 
-- Equation name is '_LC7_K43', type is buried 
_LC7_K43 = LCELL( _EQ001);
  _EQ001 =  bin0 &  bin1 & !bin2 & !bin3;

-- Node name is '~162~1' 
-- Equation name is '~162~1', location is LC8_K43, type is buried.
-- synthesized logic cell 
_LC8_K43 = LCELL( _EQ002);
  _EQ002 = !bin0 &  bin1 &  bin2 & !bin3
         #  bin0 & !bin1 &  bin2 & !bin3;

-- Node name is ':162' 
-- Equation name is '_LC5_K43', type is buried 
_LC5_K43 = LCELL( _EQ003);
  _EQ003 =  _LC8_K43 &  p
         #  _LC1_K43 &  p;

-- Node name is ':163' 
-- Equation name is '_LC8_D4', type is buried 
_LC8_D4  = LCELL( _EQ004);
  _EQ004 = !bin1 &  bin2 & !bin3
         #  bin1 & !bin2 & !bin3
         # !bin0 &  bin2 & !bin3
         # !bin1 & !bin2 &  bin3;

-- Node name is ':164' 
-- Equation name is '_LC6_K43', type is buried 
_LC6_K43 = LCELL( _EQ005);
  _EQ005 = !bin0 &  bin2 & !bin3
         # !bin0 & !bin1 & !bin2
         # !bin1 &  bin2 & !bin3
         # !bin1 & !bin2 &  bin3;

-- Node name is ':165' 
-- Equation name is '_LC2_D4', type is buried 
_LC2_D4  = LCELL( _EQ006);
  _EQ006 = !bin0 & !bin2 & !bin3
         # !bin0 &  bin1 & !bin3
         # !bin0 & !bin1 & !bin2;

-- Node name is ':166' 
-- Equation name is '_LC6_D4', type is buried 
_LC6_D4  = LCELL( _EQ007);
  _EQ007 = !bin0 & !bin2 & !bin3
         # !bin0 &  bin1 & !bin3
         # !bin0 & !bin1 & !bin2
         #  bin0 & !bin1 &  bin2 & !bin3
         #  bin1 & !bin2 & !bin3
         # !bin1 & !bin2 &  bin3;

-- Node name is ':167' 
-- Equation name is '_LC4_K43', type is buried 
_LC4_K43 = LCELL( _EQ008);
  _EQ008 =  _LC6_K43
         #  _LC2_K43
         #  _LC7_K43;

-- Node name is '~168~1' 
-- Equation name is '~168~1', location is LC2_K43, type is buried.
-- synthesized logic cell 
_LC2_K43 = LCELL( _EQ009);
  _EQ009 =  bin0 & !bin1 & !bin2 & !bin3
         #  bin0 &  bin1 &  bin2 & !bin3;

-- Node name is ':168' 
-- Equation name is '_LC1_K43', type is buried 
_LC1_K43 = LCELL( _EQ010);
  _EQ010 = !bin0 & !bin1 & !bin3
         #  bin0 &  bin1 & !bin3
         # !bin2 & !bin3
         # !bin1 & !bin2;

-- Node name is ':169' 
-- Equation name is '_LC3_K43', type is buried 
_LC3_K43 = LCELL( _EQ011);
  _EQ011 = !bin0 & !bin2 & !bin3
         #  bin1 &  bin2 & !bin3
         # !bin0 & !bin1 & !bin2
         #  bin0 &  bin2 & !bin3
         #  bin0 &  bin1 & !bin3
         # !bin1 & !bin2 &  bin3;



Project Information                          c:\maxplus2\verilog6\btoseven.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:10
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:14


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,514K