cnts.fit

verilog除頻器可用於編碼段運用可以穩定電路設計

-- MAX+plus II Compiler Fit File      
-- Version 10.1 06/12/2001            
-- Compiled: 04/19/2007 02:43:21      

-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "cnts"
BEGIN

    DEVICE = "EP1K100FC484-3";

    "en"                           : INPUT_PIN  = E12    ;
    "mclk"                         : INPUT_PIN  = D12    ;
    "cq0"                          : OUTPUT_PIN = K1     ;
    "cq1"                          : OUTPUT_PIN = H16    ;
    "cq2"                          : OUTPUT_PIN = K4     ;
    "cq3"                          : OUTPUT_PIN = J16    ;
    "s10s"                         : OUTPUT_PIN = K18    ;
    "|lpm_add_sub:64|addcore:adder|:55" : LOCATION   = LC3_E34;
    "|lpm_add_sub:64|addcore:adder|:59" : LOCATION   = LC4_E34;
    ":9"                           : LOCATION   = LC2_E34;
    ":48"                          : LOCATION   = LC7_E34;
    ":49"                          : LOCATION   = LC8_E34;
    ":50"                          : LOCATION   = LC5_E34;
    ":51"                          : LOCATION   = LC6_E34;
    ":63"                          : LOCATION   = LC1_E34;

END;

INTERNAL_INFO "cnts"
BEGIN
	DEVICE = EP1K100FC484-3;
    OD0PE12 : LORAX = "1:FB0|2:FH0R4,PA16R4C33->LC7_E34,->LC8_E34,->LC5_E34,->LC6_E34||";
    OD4PD12 : LORAX = "1:FB4->LC7_E34,->LC8_E34,->LC5_E34,->LC6_E34,->LC1_E34|";
    LC7_E34 : LORAX = "1:MSW7R4C32,G157R4->OH7R4PJ16|";
    LC8_E34 : LORAX = "1:MSW4R4C32,G161R4->OH12R4PK4|";
    LC5_E34 : LORAX = "1:MSW5R4C32,HHR67R4->OH5R4PH16|";
    LC6_E34 : LORAX = "1:MSW6R4C32,G141R4->OH14R4PK1|";
    LC1_E34 : LORAX = "1:MSW0R4C33,HHR45R4->OH0R4PK18|";
	LC3_E34 : LORAX2 = "X, X, LC5_E34, LC6_E34";
	LC4_E34 : LORAX2 = "X, LC8_E34, LC5_E34, LC6_E34";
	LC2_E34 : LORAX2 = "LC7_E34, LC5_E34, LC8_E34, LC6_E34";
	LC7_E34 : LORAX2 = "OD0PE12, LC2_E34, LC4_E34, LC7_E34";
	LC8_E34 : LORAX2 = "OD0PE12, LC2_E34, LC3_E34, LC8_E34";
	LC5_E34 : LORAX2 = "OD0PE12, LC2_E34, LC5_E34, LC6_E34";
	LC6_E34 : LORAX2 = "X, X, OD0PE12, LC6_E34";
	LC1_E34 : LORAX2 = "LC7_E34, LC5_E34, LC8_E34, LC6_E34";
END;