cntm.v

来自「verilog除頻器可用於編碼段運用可以穩定電路設計」· Verilog 代码 · 共 22 行

module cntm(clk,cq,m10m);
input clk;
output [3:0] cq;
output m10m;
reg m10m;
reg [3:0] cq;
always@(posedge clk)
begin
if(!(cq==9))
   cq<=cq+1;
else if(cq==9)
   cq<=0;
end
always@(posedge clk)
begin
if(cq==9)
   m10m=1;
else
   m10m=0;
end
endmodule