cntm2.v

verilog除頻器可用於編碼段運用可以穩定電路設計

module cntm2(clk,cq);
input clk;
output [3:0] cq;
reg [3:0] cq;
always@(posedge clk)
begin
if(!(cq==5))
   cq<=cq+1;
else if(cq==5)
   cq<=0;
end
endmodule