📄 kon.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kon is
port(clk1,k,set,reset: in std_logic;
hs,ms,ss,ht,mt,st: buffer std_logic;
sel: buffer std_logic);
end kon;
architecture konx of kon is
type sq is (s0,s1,s2,s3,s4,s5,s6,s7);
signal s: sq:=s0;
begin
cn: process (clk1,k,set,reset)
begin
if (reset='1') then
s<=s0;
elsif (clk1'event and clk1='1') then
case s is
when s0=>if(k='0'and set='1')then
s<=s1;
elsif (k='1'and set='1')then
s<=s4;
end if;
when s1=>if(k='1'and set='0')then
s<=s2;
end if;
when s2=>if(k='0'and set='1')then
s<=s3;
end if;
when s3=>if(k='1'and set='0')then
s<=s0;
end if;
when s4=>if(k='0'and set='0')then
s<=s0;
elsif (k='0'and set='1')then
s<=s5;
end if;
when s5=>if(k='1'and set='0')then
s<=s6;
end if;
when s6=>if(k='0'and set='1')then
s<=s7;
end if;
when s7=>if(k='1'and set='0')then
s<=s4;
end if;
end case;
end if;
end process cn;
cm: process (s)
begin
case s is
when s0=>hs<='0';ms<='0';ss<='0';ht<='0';mt<='0';st<='0';
sel<='1';
when s1=>hs<='1';ms<='0';ss<='0';ht<='0';mt<='0';st<='0';
sel<='1';
when s2=>hs<='0';ms<='1';ss<='0';ht<='0';mt<='0';st<='0';
sel<='1';
when s3=>hs<='0';ms<='0';ss<='1';ht<='0';mt<='0';st<='0';
sel<='1';
when s4=>hs<='0';ms<='0';ss<='0';ht<='0';mt<='0';st<='0';
sel<='0';
when s5=>hs<='0';ms<='0';ss<='0';ht<='1';mt<='0';st<='0';
sel<='0';
when s6=>hs<='0';ms<='0';ss<='0';ht<='0';mt<='1';st<='0';
sel<='0';
when s7=>hs<='0';ms<='0';ss<='0';ht<='0';mt<='0';st<='1';
sel<='0';
when others=>hs<='0';ms<='0';ss<='0';ht<='0';mt<='0';st<='0';
sel<='0';
end case;
end process cm;
end konx;
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