📄 ym8.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity ym8 is
port(a:in std_logic_vector(3 downto 0);
y:out std_logic_vector(6 downto 0));
end ym8;
architecture ym of ym8 is
signal n:std_logic_vector(3 downto 0);
begin
n<=a(3)&a(2)&a(1)&a(0);
process(n)
begin
case n is
when "0000"=>y<="1111110";
when "0001"=>y<="0110000";
when "0010"=>y<="1101101";
when "0011"=>y<="1111001";
when "0100"=>y<="0110011";
when "0101"=>y<="1011011";
when "0110"=>y<="1011111";
when "0111"=>y<="1110000";
when "1000"=>y<="1111111";
when "1001"=>y<="1111011";
when "1111"=>Y<="0000001";
when others=>y<="0000000";
end case;
end process;
end ym;
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