time.vhd

1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的调时功能 4、闹钟定时功能 5、整点报时功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity time is
   port(ch,cm,cs,f4,f1,reset:   in std_logic;
        hs,ms,ss:  buffer std_logic_vector(7 downto 4);
        hl,ml,sl:  buffer std_logic_vector(3 downto 0));
end time;
architecture timex of time is
  signal sf1,sf2,cp1,cp2,cp3:std_logic;
   begin 
    cp1<=(f1 and not cs)or(f4 and cs);
    cp2<=(sf1 and not cm)or(f4 and cm);
    cp3<=(sf2 and not ch)or(f4 and ch);
  cs1:process(reset,cp1)
    begin
	  if reset='1' then
		 ss<="0000";
         sl<="0000";
	  elsif(cp1'event and cp1='1')then
		 if(ss=5 and sl=9)then
           ss<="0000"; 
           sl<="0000";
           sf1<='1';   		
         elsif (sl=9)then
		   sl<="0000";
		   ss<=ss+1;
            sf1<='0';
		 else sl<=sl+1; 
           sf1<='0';
         end if;
       end if;
      end process cs1;
  cm1:process(cp2,reset)
    begin
	  if reset='1' then
		 ms<="0000";
         ml<="0000";
	  elsif(cp2'event and cp2='1')then      
   	     if(ms=5 and ml=9)then
           ms<="0000"; 
           ml<="0000";
           sf2<='1';
		 elsif (ml=9)then
		   ml<="0000";
		   ms<=ms+1;
		 else ml<=ml+1;
         end if;
       end if;
    end process cm1;
    ch1:process(reset,cp3)
    begin
	  if reset='1' then
		 hs<="0000";
         hl<="0000";
	  elsif(cp3'event and cp3='1')then
		if(hs=2 and hl=3)then
           hs<="0000"; 
           hl<="0000";
	    elsif (hl=9)then
		   hl<="0000";
		   hs<=hs+1;
		else hl<=hl+1;
		end if;
      end if;
   end process ch1;
 end timex;