max8_1.vhd

来自「1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
entity max8_1 is 
port (d0:in std_logic_vector(3 downto 0);
      d1:in std_logic_vector(3 downto 0);
      d2:in std_logic_vector(3 downto 0);
      d3:in std_logic_vector(3 downto 0);
      d4:in std_logic_vector(3 downto 0);
      d5:in std_logic_vector(3 downto 0);
      d6:in std_logic_vector(3 downto 0);
      d7:in std_logic_vector(3 downto 0);
      sel:in std_logic_vector(2 downto 0);
       y :out std_logic_vector(3 downto 0));
end max8_1;
architecture arch of max8_1 is
begin
process(d0,d1,d2,d3,d4,d5,d6,d7,sel)
begin 
case sel is
when "000"=>y<=d0;
when "001"=>y<=d1;
when "010"=>y<=d2;
when "011"=>y<=d3;
when "100"=>y<=d4;
when "101"=>y<=d5;
when "110"=>y<=d6;
when "111"=>y<=d7;
when  others=>y<="XXXX";
end case;
end process;
end arch;