tc.vhd

来自「1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TC is
   port(ht1,mt1,st1:   in std_logic_vector(7 downto 4);
        ht2,mt2,st2:   in std_logic_vector(3 downto 0);
        cht,cmt,cst,f4,reset:   in std_logic;
        cpt:           out std_logic;
        bh1,bm1,bs1:   buffer std_logic_vector(7 downto 4);
        bh2,bm2,bs2:   buffer std_logic_vector(3 downto 0));
end TC;
architecture TCx of TC is
 signal c1,c2,c3: std_logic;    --中间信号时、分、秒有