📄 y3_8.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity y3_8 is
port(a: in std_logic_vector(2 downto 0);
g1,g2a,g2b:in std_logic;
y: out std_logic_vector(7 downto 0));
end y3_8;
architecture rtl of y3_8 is
signal n:std_logic_vector(2 downto 0);
begin
n<=a;
process(n,g1,g2a,g2b)
begin
if(g1='1' and g2a='0' and g2b='0')then
case n is
when "000"=>y<="00000001";
when "001"=>y<="00000010";
when "010"=>y<="00000100";
when "011"=>y<="00001000";
when "100"=>y<="00010000";
when "101"=>y<="00100000";
when "110"=>y<="01000000";
when "111"=>y<="10000000";
when others=>y<="00000000";
end case;
else
y<="11111111";
end if;
end process;
end rtl;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -