fpin.vhd

来自「1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fpin is
   port(reset,clk:in std_logic;
        f1024,f512,f4,f1: buffer std_logic);
end fpin;
architecture fpinx of fpin is 
   signal q: std_logic_vector(9 downto 0);
begin 
   process(clk,reset,q)
   begin 
    if(reset='1')then
      q<="0000000000";
    elsif(clk'event and clk='1')then
      q<=q+1;
    end if;
     f1024<=clk;
     f512<=q(0);
     f4<=q(7);
     f1<=q(9);
   end process;
end fpinx;