📄 m4v8_1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity m4v8_1 is
port(a,b,c,d,e,f,g,h:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0));
end m4v8_1;
architecture arch of m4v8_1 is
begin
process(a,b,c,d,e,f,g,h,sel)
begin
case sel is
when "000"=>y<=a;
when "001"=>y<=b;
when "010"=>y<=c;
when "011"=>y<=d;
when "101"=>y<=f;
when "100"=>y<=e;
when "110"=>y<=g;
when "111"=>y<=h;
when others=>y<="0000";
end case;
end process;
end arch;
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