cnt8.vhd

来自「1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt8 is
   port(reset,clk:in std_logic;
        q: out std_logic_vector(3 downto 0));
end cnt8;
architecture behav of cnt8 is 
   signal q0:integer range 0 to 7;
begin 
   process(clk,reset,q0)
   begin 
        if(clk'event and clk='1')then
          if(reset='1')then
             q0<=0;
          else
             q0<=q0+1;
          end if;
        end if;
        q<=conv_std_logic_vector(q0,3);
   end process;
end behav;