📄 de2_usb_api.tan.rpt
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; 10.909 ns ; None ; CMD_Decode:u5|oSDR_Select[1] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[5] ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.985 ns ; 6.076 ns ;
; 10.913 ns ; None ; CMD_Decode:u5|oSDR_Select[1] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[6] ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.985 ns ; 6.072 ns ;
; 11.370 ns ; None ; CMD_Decode:u5|mSDR_WRn ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.996 ns ; 5.626 ns ;
; 11.407 ns ; None ; CMD_Decode:u5|oSDR_Select[0] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.985 ns ; 5.578 ns ;
; 11.676 ns ; None ; CMD_Decode:u5|oSDR_Select[1] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.985 ns ; 5.309 ns ;
; 11.776 ns ; None ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD ; Multi_Sdram:u3|Sdram_Controller:u1|mDONE ; OSC_50 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns ; 16.995 ns ; 5.219 ns ;
; 12.156 ns ; 127.49 MHz ( period = 7.844 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[8] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.735 ns ; 7.579 ns ;
; 12.340 ns ; 130.55 MHz ( period = 7.660 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[7] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.735 ns ; 7.395 ns ;
; 12.433 ns ; 132.15 MHz ( period = 7.567 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[6] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 7.303 ns ;
; 12.498 ns ; 133.30 MHz ( period = 7.502 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[5] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 7.238 ns ;
; 13.024 ns ; 143.35 MHz ( period = 6.976 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[2] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.729 ns ; 6.705 ns ;
; 13.068 ns ; 144.26 MHz ( period = 6.932 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[3] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.711 ns ; 6.643 ns ;
; 13.071 ns ; 144.32 MHz ( period = 6.929 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[0] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.711 ns ; 6.640 ns ;
; 13.079 ns ; 144.49 MHz ( period = 6.921 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[4] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.735 ns ; 6.656 ns ;
; 13.092 ns ; 144.76 MHz ( period = 6.908 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.644 ns ;
; 13.320 ns ; 149.70 MHz ( period = 6.680 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[8] ; Multi_Sdram:u3|Sdram_Controller:u1|Read ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.742 ns ; 6.422 ns ;
; 13.398 ns ; 151.47 MHz ( period = 6.602 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[6] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.711 ns ; 6.313 ns ;
; 13.450 ns ; 152.67 MHz ( period = 6.550 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[2] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.712 ns ; 6.262 ns ;
; 13.451 ns ; 152.70 MHz ( period = 6.549 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[7] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.712 ns ; 6.261 ns ;
; 13.451 ns ; 152.70 MHz ( period = 6.549 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.712 ns ; 6.261 ns ;
; 13.455 ns ; 152.79 MHz ( period = 6.545 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[4] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.714 ns ; 6.259 ns ;
; 13.461 ns ; 152.93 MHz ( period = 6.539 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[3] ; Multi_Sdram:u3|Sdram_Controller:u1|ST[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.735 ns ; 6.274 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[1] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[11] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[9] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[10] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[6] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[5] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[7] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[2] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[4] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[12] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[8] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[14] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[15] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.467 ns ; 153.07 MHz ( period = 6.533 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[3] ; Multi_Sdram:u3|Sdram_Controller:u1|control_interface:control1|init_timer[13] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.736 ns ; 6.269 ns ;
; 13.479 ns ; 153.35 MHz ( period = 6.521 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[8] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[3] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000 ns ; 19.717 ns ; 6.238 ns ;
; 13.482 ns ; 153.42 MHz ( period = 6.518 ns ) ; Multi_Sdram:u3|Sdram_Controller:u1|ST[8] ; Multi_Sdram:u3|Sdram_Controller:u1|SA[0] ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 20.000⌨️ 快捷键说明
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