de2_usb_api.tan.rpt

来自「Altera de2开发板提供的配套软件程序」· RPT 代码 · 共 203 行 · 第 1/5 页

without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+
; Type                                                                                            ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                            ; To                                                          ; From Clock                                                                       ; To Clock                                                                         ; Failed Paths ;
+-------------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                                  ; N/A       ; None                             ; 13.593 ns                        ; SRAM_DQ[6]                                                                                                                                      ; VGA_Controller:u8|Cur_Color_G[8]                            ; --                                                                               ; OSC_27                                                                           ; 0            ;
; Worst-case tco                                                                                  ; N/A       ; None                             ; 22.366 ns                        ; AUDIO_DAC:u11|SEL_Cont[1]                                                                                                                       ; AUD_DACDAT                                                  ; OSC_27                                                                           ; --                                                                               ; 0            ;
; Worst-case tpd                                                                                  ; N/A       ; None                             ; 15.942 ns                        ; DPDT_SW[1]                                                                                                                                      ; AUD_DACDAT                                                  ; --                                                                               ; --                                                                               ; 0            ;
; Worst-case th                                                                                   ; N/A       ; None                             ; -2.100 ns                        ; I2C_SDAT                                                                                                                                        ; I2C_AV_Config:u10|I2C_Controller:u0|ACK3                    ; --                                                                               ; OSC_50                                                                           ; 0            ;
; Clock Setup: 'OSC_50'                                                                           ; 1.502 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; Multi_Sdram:u3|Sdram_Controller:u1|mDONE                                                                                                        ; Multi_Sdram:u3|Sdram_Controller:u1|Pre_DONE                 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; OSC_50                                                                           ; 0            ;
; Clock Setup: 'Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0' ; 8.547 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD                                                                                                     ; Multi_Sdram:u3|Sdram_Controller:u1|Read                     ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'                                   ; 23.808 ns ; 18.00 MHz ( period = 55.555 ns ) ; 125.94 MHz ( period = 7.940 ns ) ; AUDIO_DAC:u11|FLASH_Cont[0]                                                                                                                     ; AUDIO_DAC:u11|FLASH_Out_Tmp[0]                              ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1                                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1                                   ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'                                   ; 24.231 ns ; 25.20 MHz ( period = 39.682 ns ) ; 64.72 MHz ( period = 15.451 ns ) ; VGA_OSD_RAM:u9|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_q7o1:auto_generated|altsyncram_p132:altsyncram1|ram_block2a2~PORTADATAOUT6 ; VGA_OSD_RAM:u9|oRed[8]                                      ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0                                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0                                   ; 0            ;
; Clock Setup: 'TCK'                                                                              ; N/A       ; None                             ; 151.08 MHz ( period = 6.619 ns ) ; USB_JTAG:u1|JTAG_TRANS:u1|rCont[1]                                                                                                              ; USB_JTAG:u1|JTAG_TRANS:u1|TDO                               ; TCK                                                                              ; TCK                                                                              ; 0            ;
; Clock Hold: 'OSC_50'                                                                            ; -3.444 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; I2C_AV_Config:u10|LUT_INDEX[5]                                                                                                                  ; I2C_AV_Config:u10|LUT_DATA[4]                               ; OSC_50                                                                           ; OSC_50                                                                           ; 96           ;
; Clock Hold: 'Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag                                                                                     ; Multi_Sdram:u3|Sdram_Controller:u1|command:command1|rw_flag ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk0'                                    ; 0.499 ns  ; 25.20 MHz ( period = 39.682 ns ) ; N/A                              ; VGA_Controller:u8|oVGA_V_SYNC                                                                                                                   ; VGA_Controller:u8|oVGA_V_SYNC                               ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0                                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0                                   ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'                                    ; 0.499 ns  ; 18.00 MHz ( period = 55.555 ns ) ; N/A                              ; AUDIO_DAC:u11|SEL_Cont[2]                                                                                                                       ; AUDIO_DAC:u11|SEL_Cont[2]                                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1                                   ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1                                   ; 0            ;
; Total number of failed paths                                                                    ;           ;                                  ;                                  ;                                                                                                                                                 ;                                                             ;                                                                                  ;                                                                                  ; 96           ;
+-------------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;