de2_usb_api.tan.rpt

Altera de2开发板提供的配套软件程序

; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                                  ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; OSC_50   ; 1                     ; 1                   ; -2.784 ns ;              ;
; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk2 ;                    ; PLL output ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; OSC_50   ; 1                     ; 1                   ; -2.784 ns ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk0                                   ;                    ; PLL output ; 25.2 MHz         ; 0.000 ns      ; 0.000 ns     ; OSC_27   ; 14                    ; 15                  ; -2.790 ns ;              ;
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1                                   ;                    ; PLL output ; 18.0 MHz         ; 0.000 ns      ; 0.000 ns     ; OSC_27   ; 2                     ; 3                   ; -2.790 ns ;              ;
; OSC_50                                                                           ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; OSC_27                                                                           ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; TCK                                                                              ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                        ; To                                                                           ; From Clock                                                                       ; To Clock                                                                         ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 8.547 ns                                ; None                                                ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD                                 ; Multi_Sdram:u3|Sdram_Controller:u1|Read                                      ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.995 ns                 ; 8.448 ns                ;
; 8.599 ns                                ; None                                                ; CMD_Decode:u5|mSDR_Start                                                    ; Multi_Sdram:u3|Sdram_Controller:u1|Read                                      ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.996 ns                 ; 8.397 ns                ;
; 8.734 ns                                ; None                                                ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD                                 ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0]                                     ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.995 ns                 ; 8.261 ns                ;
; 8.743 ns                                ; None                                                ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD                                 ; Multi_Sdram:u3|Sdram_Controller:u1|CMD[1]                                    ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.994 ns                 ; 8.251 ns                ;
; 8.743 ns                                ; None                                                ; Multi_Sdram:u3|Sdram_Multiplexer:u0|mSDR_RD                                 ; Multi_Sdram:u3|Sdram_Controller:u1|CMD[0]                                    ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.994 ns                 ; 8.251 ns                ;
; 8.786 ns                                ; None                                                ; CMD_Decode:u5|mSDR_Start                                                    ; Multi_Sdram:u3|Sdram_Controller:u1|ST[0]                                     ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.996 ns                 ; 8.210 ns                ;
; 8.795 ns                                ; None                                                ; CMD_Decode:u5|mSDR_Start                                                    ; Multi_Sdram:u3|Sdram_Controller:u1|CMD[1]                                    ; OSC_50                                                                           ; Multi_Sdram:u3|Sdram_Controller:u1|PLL1:sdram_pll1|altpll:altpll_component|_clk0 ; 17.216 ns                   ; 16.995 ns                 ; 8.200 ns                ;