📄 master_control_main.tan.qmsg

📁 Verilog HDL数字控制系统设计实例
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_1Hz register Door_Control:inst\|CNT\[0\] register Door_Control:inst\|CNT\[0\] 126.58 MHz 7.9 ns Internal " "Info: Clock \"Clock_1Hz\" has Internal fmax of 126.58 MHz between source register \"Door_Control:inst\|CNT\[0\]\" and destination register \"Door_Control:inst\|CNT\[0\]\" (period= 7.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Longest register register " "Info: + Longest register to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Door_Control:inst\|CNT\[0\] 1 REG LC26 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.400 ns Door_Control:inst\|CNT~226 2 COMB LC25 1 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.400 ns; Loc. = LC25; Fanout = 1; COMB Node = 'Door_Control:inst\|CNT~226'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "4.400 ns" { Door_Control:inst|CNT[0] Door_Control:inst|CNT~226 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.500 ns Door_Control:inst\|CNT\[0\] 3 REG LC26 15 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 5.500 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "1.100 ns" { Door_Control:inst|CNT~226 Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 74.55 % " "Info: Total cell delay = 4.100 ns ( 74.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 25.45 % " "Info: Total interconnect delay = 1.400 ns ( 25.45 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.500 ns" { Door_Control:inst|CNT[0] Door_Control:inst|CNT~226 Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { Door_Control:inst|CNT[0] Door_Control:inst|CNT~226 Door_Control:inst|CNT[0] } { 0.000ns 1.400ns 0.000ns } { 0.000ns 3.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clock_1Hz 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 248 -240 -72 264 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Door_Control:inst\|CNT\[0\] 2 REG LC26 15 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"Clock_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clock_1Hz 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 248 -240 -72 264 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Door_Control:inst\|CNT\[0\] 2 REG LC26 15 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.500 ns" { Door_Control:inst|CNT[0] Door_Control:inst|CNT~226 Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.500 ns" { Door_Control:inst|CNT[0] Door_Control:inst|CNT~226 Door_Control:inst|CNT[0] } { 0.000ns 1.400ns 0.000ns } { 0.000ns 3.000ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\] Master_Floor3 Floor_Time 21.000 ns register " "Info: tsu for register \"Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\]\" (data pin = \"Master_Floor3\", clock pin = \"Floor_Time\") is 21.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.200 ns + Longest pin register " "Info: + Longest pin to register delay is 22.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Master_Floor3 1 PIN PIN_50 14 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_50; Fanout = 14; PIN Node = 'Master_Floor3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Master_Floor3 } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 784 8 176 800 "Master_Floor3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.000 ns) 5.800 ns Lift_Run_Manage:inst2\|always0~1177 2 COMB LC10 2 " "Info: 2: + IC(1.600 ns) + CELL(4.000 ns) = 5.800 ns; Loc. = LC10; Fanout = 2; COMB Node = 'Lift_Run_Manage:inst2\|always0~1177'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.600 ns" { Master_Floor3 Lift_Run_Manage:inst2|always0~1177 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.000 ns) 11.200 ns Lift_Run_Manage:inst2\|always0~1190 3 COMB LC45 3 " "Info: 3: + IC(1.400 ns) + CELL(4.000 ns) = 11.200 ns; Loc. = LC45; Fanout = 3; COMB Node = 'Lift_Run_Manage:inst2\|always0~1190'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.400 ns" { Lift_Run_Manage:inst2|always0~1177 Lift_Run_Manage:inst2|always0~1190 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.400 ns) 16.600 ns Lift_Run_Manage:inst2\|Up_En~30 4 COMB LOOP LC7 21 " "Info: 4: + IC(0.000 ns) + CELL(5.400 ns) = 16.600 ns; Loc. = LC7; Fanout = 21; COMB LOOP Node = 'Lift_Run_Manage:inst2\|Up_En~30'" { { "Info" "ITDB_PART_OF_SCC" "Lift_Run_Manage:inst2\|Up_En~30 LC7 " "Info: Loc. = LC7; Node \"Lift_Run_Manage:inst2\|Up_En~30\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.400 ns" { Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 21.100 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\]~1805 5 COMB LC36 1 " "Info: 5: + IC(1.500 ns) + CELL(3.000 ns) = 21.100 ns; Loc. = LC36; Fanout = 1; COMB Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\]~1805'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "4.500 ns" { Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 22.200 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 6 REG LC37 70 " "Info: 6: + IC(0.000 ns) + CELL(1.100 ns) = 22.200 ns; Loc. = LC37; Fanout = 70; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "1.100 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.700 ns 79.73 % " "Info: Total cell delay = 17.700 ns ( 79.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns 20.27 % " "Info: Total interconnect delay = 4.500 ns ( 20.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "22.200 ns" { Master_Floor3 Lift_Run_Manage:inst2|always0~1177 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "22.200 ns" { Master_Floor3 Master_Floor3~out Lift_Run_Manage:inst2|always0~1177 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.600ns 1.400ns 0.000ns 1.500ns 0.000ns } { 0.000ns 0.200ns 4.000ns 4.000ns 5.400ns 3.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"Floor_Time\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Floor_Time 1 CLK PIN_90 6 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_90; Fanout = 6; CLK Node = 'Floor_Time'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 664 -240 -72 680 "Floor_Time" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 2 REG LC37 70 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC37; Fanout = 70; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "22.200 ns" { Master_Floor3 Lift_Run_Manage:inst2|always0~1177 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "22.200 ns" { Master_Floor3 Master_Floor3~out Lift_Run_Manage:inst2|always0~1177 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0]~1805 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.600ns 1.400ns 0.000ns 1.500ns 0.000ns } { 0.000ns 0.200ns 4.000ns 4.000ns 5.400ns 3.000ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_1Hz Door_On_Off Door_Control:inst\|CNT\[0\] 11.600 ns register " "Info: tco from clock \"Clock_1Hz\" to destination pin \"Door_On_Off\" through register \"Door_Control:inst\|CNT\[0\]\" is 11.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Clock_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clock_1Hz 1 CLK PIN_87 3 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_87; Fanout = 3; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 248 -240 -72 264 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Door_Control:inst\|CNT\[0\] 2 REG LC26 15 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Clock_1Hz Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out Door_Control:inst|CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register pin " "Info: + Longest register to pin delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Door_Control:inst\|CNT\[0\] 1 REG LC26 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 15; REG Node = 'Door_Control:inst\|CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Door_Control:inst|CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.400 ns Door_Control:inst\|Door_on_off~219 2 COMB LC27 1 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.400 ns; Loc. = LC27; Fanout = 1; COMB Node = 'Door_Control:inst\|Door_on_off~219'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "4.400 ns" { Door_Control:inst|CNT[0] Door_Control:inst|Door_on_off~219 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 5.500 ns Door_Control:inst\|Door_on_off~223 3 COMB LC28 1 " "Info: 3: + IC(0.000 ns) + CELL(1.100 ns) = 5.500 ns; Loc. = LC28; Fanout = 1; COMB Node = 'Door_Control:inst\|Door_on_off~223'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "1.100 ns" { Door_Control:inst|Door_on_off~219 Door_Control:inst|Door_on_off~223 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 7.600 ns Door_Control:inst\|Door_on_off~218 4 COMB LC29 1 " "Info: 4: + IC(0.000 ns) + CELL(2.100 ns) = 7.600 ns; Loc. = LC29; Fanout = 1; COMB Node = 'Door_Control:inst\|Door_on_off~218'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.100 ns" { Door_Control:inst|Door_on_off~223 Door_Control:inst|Door_on_off~218 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Door_Control.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 8.000 ns Door_On_Off 5 PIN PIN_6 0 " "Info: 5: + IC(0.000 ns) + CELL(0.400 ns) = 8.000 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'Door_On_Off'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.400 ns" { Door_Control:inst|Door_on_off~218 Door_On_Off } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 216 648 824 232 "Door_On_Off" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns 82.50 % " "Info: Total cell
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