📄 master_control_main.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Lift_Run_Manage:inst2\|Up_En~30 " "Info: Node \"Lift_Run_Manage:inst2\|Up_En~30\"" { } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } } } 0} } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Floor_Time " "Info: Assuming node \"Floor_Time\" is an undefined clock" { } { { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 664 -240 -72 680 "Floor_Time" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Floor_Time" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_1Hz " "Info: Assuming node \"Clock_1Hz\" is an undefined clock" { } { { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 248 -240 -72 264 "Clock_1Hz" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_1Hz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Floor_Time register Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\] register Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 40.65 MHz 24.6 ns Internal " "Info: Clock \"Floor_Time\" has Internal fmax of 40.65 MHz between source register \"Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\]\" and destination register \"Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\]\" (period= 24.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.200 ns + Longest register register " "Info: + Longest register to register delay is 22.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\] 1 REG LC1 87 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 87; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.000 ns) 5.800 ns Lift_Run_Manage:inst2\|always0~1161 2 COMB LC32 2 " "Info: 2: + IC(1.800 ns) + CELL(4.000 ns) = 5.800 ns; Loc. = LC32; Fanout = 2; COMB Node = 'Lift_Run_Manage:inst2\|always0~1161'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.800 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] Lift_Run_Manage:inst2|always0~1161 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.000 ns) 11.200 ns Lift_Run_Manage:inst2\|always0~1190 3 COMB LC45 3 " "Info: 3: + IC(1.400 ns) + CELL(4.000 ns) = 11.200 ns; Loc. = LC45; Fanout = 3; COMB Node = 'Lift_Run_Manage:inst2\|always0~1190'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.400 ns" { Lift_Run_Manage:inst2|always0~1161 Lift_Run_Manage:inst2|always0~1190 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.400 ns) 16.600 ns Lift_Run_Manage:inst2\|Up_En~30 4 COMB LOOP LC7 21 " "Info: 4: + IC(0.000 ns) + CELL(5.400 ns) = 16.600 ns; Loc. = LC7; Fanout = 21; COMB LOOP Node = 'Lift_Run_Manage:inst2\|Up_En~30'" { { "Info" "ITDB_PART_OF_SCC" "Lift_Run_Manage:inst2\|Up_En~30 LC7 " "Info: Loc. = LC7; Node \"Lift_Run_Manage:inst2\|Up_En~30\"" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "5.400 ns" { Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 52 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 21.100 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\]~1809 5 COMB LC34 1 " "Info: 5: + IC(1.500 ns) + CELL(3.000 ns) = 21.100 ns; Loc. = LC34; Fanout = 1; COMB Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\]~1809'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "4.500 ns" { Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 22.200 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 6 REG LC35 70 " "Info: 6: + IC(0.000 ns) + CELL(1.100 ns) = 22.200 ns; Loc. = LC35; Fanout = 70; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "1.100 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.500 ns 78.83 % " "Info: Total cell delay = 17.500 ns ( 78.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 21.17 % " "Info: Total interconnect delay = 4.700 ns ( 21.17 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "22.200 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] Lift_Run_Manage:inst2|always0~1161 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "22.200 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] Lift_Run_Manage:inst2|always0~1161 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 1.800ns 1.400ns 0.000ns 1.500ns 0.000ns } { 0.000ns 4.000ns 4.000ns 5.400ns 3.000ns 1.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Floor_Time\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Floor_Time 1 CLK PIN_90 6 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_90; Fanout = 6; CLK Node = 'Floor_Time'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 664 -240 -72 680 "Floor_Time" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 2 REG LC35 70 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC35; Fanout = 70; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[1\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"Floor_Time\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Floor_Time 1 CLK PIN_90 6 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_90; Fanout = 6; CLK Node = 'Floor_Time'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Master_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Master_Control_Main.bdf" { { 664 -240 -72 680 "Floor_Time" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\] 2 REG LC1 87 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC1; Fanout = 87; REG Node = 'Motor_Control:inst3\|lpm_counter:Now_Floor_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "0.600 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "22.200 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] Lift_Run_Manage:inst2|always0~1161 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "22.200 ns" { Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] Lift_Run_Manage:inst2|always0~1161 Lift_Run_Manage:inst2|always0~1190 Lift_Run_Manage:inst2|Up_En~30 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1]~1809 Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 1.800ns 1.400ns 0.000ns 1.500ns 0.000ns } { 0.000ns 4.000ns 4.000ns 5.400ns 3.000ns 1.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main_cmp.qrpt" Compiler "Master_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/db/Master_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/" "" "2.200 ns" { Floor_Time Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Motor_Control:inst3|lpm_counter:Now_Floor_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0}
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