hour_counter.map.qmsg

Verilog HDL数字控制系统设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 16:26:20 2006 " "Info: Processing started: Sat Jul 15 16:26:20 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off hour_counter -c hour_counter " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off hour_counter -c hour_counter" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour_counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file hour_counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 hour_counter " "Info: Found entity 1: hour_counter" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "hour_data1\[0\]~24 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"hour_data1\[0\]~24\"" {  } { { "hour_counter.v" "hour_data1\[0\]~24" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 9 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "hour_data0\[0\]~16 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"hour_data0\[0\]~16\"" {  } { { "hour_counter.v" "hour_data0\[0\]~16" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lpm_counter:hour_data1_rtl_0\|dffs\[3\] data_in GND " "Warning: Reduced register \"lpm_counter:hour_data1_rtl_0\|dffs\[3\]\" with stuck data_in port to stuck value GND" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lpm_counter:hour_data1_rtl_0\|dffs\[2\] data_in GND " "Warning: Reduced register \"lpm_counter:hour_data1_rtl_0\|dffs\[2\]\" with stuck data_in port to stuck value GND" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "hour_data1\[3\] GND " "Warning: Pin \"hour_data1\[3\]\" stuck at GND" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 9 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "hour_data1\[2\] GND " "Warning: Pin \"hour_data1\[2\]\" stuck at GND" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW1 " "Warning: No output dependent on input pin \"SW1\"" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 12 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "SW2 " "Warning: No output dependent on input pin \"SW2\"" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/timepiece/hour_counter/hour_counter.v" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "11 " "Info: Implemented 11 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 16:26:33 2006 " "Info: Processing ended: Sat Jul 15 16:26:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}