📄 rom.rpt
字号:
-- Equation name is '_LC5_A13', type is buried
!_LC5_A13 = _LC5_A13~NOT;
_LC5_A13~NOT = LCELL( _EQ027);
_EQ027 = !A0 & _LC6_A17
# _LC5_A17 & !_LC6_A17
# !A0 & _LC5_A17
# !_LC5_A24 & !_LC6_A17
# !A0 & !_LC5_A24;
-- Node name is '|CPUROM:85|:480'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ028);
_EQ028 = !A1 & A3 & !_LC1_A21
# _LC2_A13;
-- Node name is '|CPUROM:85|:510'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ029);
_EQ029 = _LC4_A19 & !_LC7_A23 & !_LC8_A15
# _LC4_A17;
-- Node name is '|CPUROM:85|~512~1'
-- Equation name is '_LC3_A13', type is buried
-- synthesized logic cell
_LC3_A13 = LCELL( _EQ030);
_EQ030 = !A4 & !_LC2_A14
# A0 & !_LC2_A14
# !_LC2_A14 & !_LC2_A15;
-- Node name is '|CPUROM:85|~512~2'
-- Equation name is '_LC4_A19', type is buried
-- synthesized logic cell
_LC4_A19 = LCELL( _EQ031);
_EQ031 = _LC3_A13 & _LC3_A22 & !_LC6_A15;
-- Node name is '|CPUROM:85|:527'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ032);
_EQ032 = !_LC2_A23 & !_LC5_A17 & _LC5_A19
# _LC1_A20 & !_LC5_A17;
-- Node name is '|CPUROM:85|:530'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = LCELL( _EQ033);
_EQ033 = A0 & !A4 & _LC2_A17
# !_LC2_A17 & _LC7_A19
# A4 & _LC7_A19
# A0 & _LC7_A19;
-- Node name is '|CPUROM:85|:1160'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ034);
_EQ034 = A3 & !_LC2_A13 & !_LC6_A22 & !_LC8_A22;
-- Node name is '|CPUROM:85|~1223~1'
-- Equation name is '_LC2_A16', type is buried
-- synthesized logic cell
_LC2_A16 = LCELL( _EQ035);
_EQ035 = _LC3_A16 & _LC8_A24;
-- Node name is '|CPUROM:85|:1223'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ036);
_EQ036 = _LC3_A16 & _LC6_A15 & _LC8_A24
# _LC3_A16 & _LC6_A23 & _LC8_A24;
-- Node name is '|CPUROM:85|:1277'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ037);
_EQ037 = !_LC2_A23 & _LC3_A23 & !_LC6_A15
# !_LC2_A23 & _LC4_A17;
-- Node name is '|CPUROM:85|:1328'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ038);
_EQ038 = _LC1_A13 & !_LC7_A23 & !_LC8_A15
# _LC2_A14 & !_LC7_A23 & !_LC8_A15;
-- Node name is '|CPUROM:85|:1337'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ039);
_EQ039 = _LC3_A23 & !_LC4_A13
# !_LC4_A13 & _LC6_A15
# !_LC4_A13 & _LC4_A17;
-- Node name is '|CPUROM:85|:1338'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ040);
_EQ040 = _LC6_A16
# A4 & !_LC3_A17
# _LC1_A20;
-- Node name is '|CPUROM:85|:1349'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ041);
_EQ041 = _LC3_A16 & !_LC5_A17 & _LC7_A16;
-- Node name is '|CPUROM:85|:1365'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ042);
_EQ042 = A4 & _LC2_A15;
-- Node name is '|CPUROM:85|~1412~1'
-- Equation name is '_LC8_A24', type is buried
-- synthesized logic cell
_LC8_A24 = LCELL( _EQ043);
_EQ043 = !_LC1_A20 & !_LC5_A17;
-- Node name is '|CPUROM:85|~1412~2'
-- Equation name is '_LC8_A23', type is buried
-- synthesized logic cell
_LC8_A23 = LCELL( _EQ044);
_EQ044 = _LC1_A13 & !_LC2_A14 & !_LC3_A19 & !_LC6_A23;
-- Node name is '|CPUROM:85|:1412'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ045);
_EQ045 = _LC2_A16 & !_LC4_A23 & !_LC7_A23 & _LC8_A23;
-- Node name is '|CPUROM:85|:1455'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ046);
_EQ046 = _LC6_A15
# _LC4_A17;
-- Node name is '|CPUROM:85|:1472'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ047);
_EQ047 = !_LC2_A23 & _LC3_A19 & !_LC5_A17
# _LC1_A20 & !_LC5_A17;
-- Node name is '|CPUROM:85|:1488'
-- Equation name is '_LC5_A22', type is buried
!_LC5_A22 = _LC5_A22~NOT;
_LC5_A22~NOT = LCELL( _EQ048);
_EQ048 = !_LC3_A22 & !_LC6_A22 & _LC8_A22
# !A3 & !_LC3_A22 & !_LC6_A22;
-- Node name is '|CPUROM:85|:1512'
-- Equation name is '_LC8_A19', type is buried
!_LC8_A19 = _LC8_A19~NOT;
_LC8_A19~NOT = LCELL( _EQ049);
_EQ049 = !_LC5_A22 & !_LC7_A23 & !_LC8_A15
# !_LC3_A13 & !_LC7_A23 & !_LC8_A15;
-- Node name is '|CPUROM:85|:1524'
-- Equation name is '_LC2_A19', type is buried
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ050);
_EQ050 = !_LC2_A23 & !_LC4_A17 & !_LC8_A19
# !_LC2_A23 & !_LC4_A17 & _LC6_A15;
-- Node name is '|CPUROM:85|:1538'
-- Equation name is '_LC4_A24', type is buried
!_LC4_A24 = _LC4_A24~NOT;
_LC4_A24~NOT = LCELL( _EQ051);
_EQ051 = !_LC2_A19
# A0 & _LC6_A17
# !_LC8_A24;
-- Node name is '|modif:86|:46' from file "modif.tdf" line 9, column 29
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ052);
_EQ052 = !A0 & !_LC1_A24 & _LC6_A17
# !_LC1_A24 & _LC4_A24
# _LC1_A24 & !_LC4_A24;
-- Node name is '|modif:86|:48' from file "modif.tdf" line 9, column 29
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ053);
_EQ053 = !_LC1_A24 & !_LC6_A17 & _LC7_A24
# A0 & !_LC1_A24 & _LC6_A17
# A0 & !_LC1_A24 & _LC7_A24;
-- Node name is '|modif:86|~58~1' from file "modif.tdf" line 9, column 29
-- Equation name is '_LC3_A16', type is buried
-- synthesized logic cell
_LC3_A16 = LCELL(!_LC6_A17);
-- Node name is '|modif:86|:58' from file "modif.tdf" line 9, column 29
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ054);
_EQ054 = _LC1_A24 & _LC8_A16
# _LC1_A24 & !_LC8_A24
# _LC3_A16 & _LC8_A16
# _LC3_A16 & !_LC8_A24;
-- Node name is '|OR5:39|:1' = '|OR5:39|OUT'
-- Equation name is '_LC8_A15', type is buried
!_LC8_A15 = _LC8_A15~NOT;
_LC8_A15~NOT = LCELL( _EQ055);
_EQ055 = _LC1_A22 & !_LC4_A22 & !_LC7_A15;
-- Node name is '|OR5:39|~1~1' = '|OR5:39|OUT~1'
-- Equation name is '_LC1_A22', type is buried
-- synthesized logic cell
_LC1_A22 = LCELL( _EQ056);
_EQ056 = A1
# A3
# _LC1_A21 & !_LC4_A15;
-- Node name is '|OR5:39|~1~2' = '|OR5:39|OUT~2'
-- Equation name is '_LC3_A15', type is buried
-- synthesized logic cell
!_LC3_A15 = _LC3_A15~NOT;
_LC3_A15~NOT = LCELL( _EQ057);
_EQ057 = _LC1_A22 & !_LC4_A22 & !_LC7_A15;
-- Node name is '|OR5:39|~1~3' = '|OR5:39|OUT~3'
-- Equation name is '_LC5_A15', type is buried
-- synthesized logic cell
!_LC5_A15 = _LC5_A15~NOT;
_LC5_A15~NOT = LCELL( _EQ058);
_EQ058 = _LC1_A22 & !_LC4_A22 & !_LC7_A15;
-- Node name is '|OR5:39|~1~4' = '|OR5:39|OUT~4'
-- Equation name is '_LC1_A15', type is buried
-- synthesized logic cell
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ059);
_EQ059 = _LC1_A22 & !_LC4_A22 & !_LC7_A15;
-- Node name is ':35'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = LCELL( _EQ060);
_EQ060 = !A1 & !A3 & _LC4_A15
# A1 & !A3 & !_LC1_A21;
-- Node name is ':36'
-- Equation name is '_LC4_A22', type is buried
!_LC4_A22 = _LC4_A22~NOT;
_LC4_A22~NOT = LCELL( _EQ061);
_EQ061 = A3
# !_LC4_A15 & _LC8_A22
# !A1 & _LC8_A22;
-- Node name is ':45'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ062);
_EQ062 = _LC7_A19
# _LC6_A22
# _LC6_A17;
-- Node name is ':46'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ063);
_EQ063 = _LC8_A15
# _LC4_A13;
-- Node name is ':77'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ064);
_EQ064 = _LC6_A22
# _LC4_A13
# _LC5_A17
# _LC4_A16;
-- Node name is ':80'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ065);
_EQ065 = _LC2_A14 & z;
-- Node name is ':90'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ066);
_EQ066 = _LC4_A16
# _LC5_A13;
Project Information d:\maxplus2\cpu_design\cpu_module\rom.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,897K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -