📄 rom.rpt
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Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\rom.rpt
rom
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 0/ 48( 0%) 27/ 48( 56%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\rom.rpt
rom
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
z : INPUT;
-- Node name is 'alu_bus'
-- Equation name is 'alu_bus', type is output
alu_bus = !_LC1_A15;
-- Node name is 'ar0'
-- Equation name is 'ar0', type is output
ar0 = _LC3_A24;
-- Node name is 'ar1'
-- Equation name is 'ar1', type is output
ar1 = _LC2_A24;
-- Node name is 'ar2'
-- Equation name is 'ar2', type is output
ar2 = _LC1_A23;
-- Node name is 'ar3'
-- Equation name is 'ar3', type is output
ar3 = _LC5_A16;
-- Node name is 'ar4'
-- Equation name is 'ar4', type is output
ar4 = _LC1_A16;
-- Node name is 'EN_IO'
-- Equation name is 'EN_IO', type is output
EN_IO = _LC7_A22;
-- Node name is 'ENLD'
-- Equation name is 'ENLD', type is output
ENLD = _LC4_A23;
-- Node name is 'ldar'
-- Equation name is 'ldar', type is output
ldar = _LC8_A13;
-- Node name is 'LDDR'
-- Equation name is 'LDDR', type is output
LDDR = _LC7_A17;
-- Node name is 'lddr1'
-- Equation name is 'lddr1', type is output
lddr1 = _LC5_A15;
-- Node name is 'lddr2'
-- Equation name is 'lddr2', type is output
lddr2 = _LC3_A15;
-- Node name is 'LDIR'
-- Equation name is 'LDIR', type is output
LDIR = _LC5_A17;
-- Node name is 'move'
-- Equation name is 'move', type is output
move = _LC2_A14;
-- Node name is 'pc_bus'
-- Equation name is 'pc_bus', type is output
pc_bus = !_LC5_A13;
-- Node name is 'p1'
-- Equation name is 'p1', type is output
p1 = _LC1_A17;
-- Node name is 'R_BUS'
-- Equation name is 'R_BUS', type is output
R_BUS = !_LC5_A23;
-- Node name is 'rd'
-- Equation name is 'rd', type is output
rd = _LC7_A13;
-- Node name is 'r_load'
-- Equation name is 'r_load', type is output
r_load = _LC8_A15;
-- Node name is 'sw_bus'
-- Equation name is 'sw_bus', type is output
sw_bus = !_LC6_A24;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC4_A22;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC2_A22;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC7_A15;
-- Node name is 'we'
-- Equation name is 'we', type is output
we = _LC7_A23;
-- Node name is '161clrn'
-- Equation name is '161clrn', type is output
161clrn = VCC;
-- Node name is '161load'
-- Equation name is '161load', type is output
161load = _LC6_A19;
-- Node name is '161pc'
-- Equation name is '161pc', type is output
161pc = _LC1_A19;
-- Node name is '|CPUROM:85|:96'
-- Equation name is '_LC6_A24', type is buried
!_LC6_A24 = _LC6_A24~NOT;
_LC6_A24~NOT = LCELL( _EQ001);
_EQ001 = !_LC6_A17
# A0;
-- Node name is '|CPUROM:85|~102~1'
-- Equation name is '_LC6_A17', type is buried
-- synthesized logic cell
!_LC6_A17 = _LC6_A17~NOT;
_LC6_A17~NOT = LCELL( _EQ002);
_EQ002 = !_LC2_A17
# A4;
-- Node name is '|CPUROM:85|~108~1'
-- Equation name is '_LC7_A17', type is buried
-- synthesized logic cell
!_LC7_A17 = _LC7_A17~NOT;
_LC7_A17~NOT = LCELL( _EQ003);
_EQ003 = A3
# _LC8_A17
# A4;
-- Node name is '|CPUROM:85|~108~2'
-- Equation name is '_LC1_A17', type is buried
-- synthesized logic cell
!_LC1_A17 = _LC1_A17~NOT;
_LC1_A17~NOT = LCELL( _EQ004);
_EQ004 = A3
# _LC8_A17
# A4;
-- Node name is '|CPUROM:85|:108'
-- Equation name is '_LC5_A17', type is buried
!_LC5_A17 = _LC5_A17~NOT;
_LC5_A17~NOT = LCELL( _EQ005);
_EQ005 = A3
# _LC8_A17
# A4;
-- Node name is '|CPUROM:85|~114~1'
-- Equation name is '_LC2_A17', type is buried
-- synthesized logic cell
!_LC2_A17 = _LC2_A17~NOT;
_LC2_A17~NOT = LCELL( _EQ006);
_EQ006 = A2
# A1
# A3;
-- Node name is '|CPUROM:85|:114'
-- Equation name is '_LC1_A20', type is buried
!_LC1_A20 = _LC1_A20~NOT;
_LC1_A20~NOT = LCELL( _EQ007);
_EQ007 = !_LC2_A17
# !_LC6_A13;
-- Node name is '|CPUROM:85|:120'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ008);
_EQ008 = A4 & !_LC3_A17;
-- Node name is '|CPUROM:85|:126'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ009);
_EQ009 = A0 & !A4 & _LC2_A15;
-- Node name is '|CPUROM:85|:132'
-- Equation name is '_LC4_A17', type is buried
!_LC4_A17 = _LC4_A17~NOT;
_LC4_A17~NOT = LCELL( _EQ010);
_EQ010 = !A4
# A3
# _LC8_A17;
-- Node name is '|CPUROM:85|:138'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ011);
_EQ011 = A1 & !A2 & A3 & _LC6_A13;
-- Node name is '|CPUROM:85|~144~1'
-- Equation name is '_LC8_A17', type is buried
-- synthesized logic cell
_LC8_A17 = LCELL( _EQ012);
_EQ012 = A0
# A2
# !A1;
-- Node name is '|CPUROM:85|~144~2'
-- Equation name is '_LC3_A17', type is buried
-- synthesized logic cell
!_LC3_A17 = _LC3_A17~NOT;
_LC3_A17~NOT = LCELL( _EQ013);
_EQ013 = A3 & !_LC8_A17;
-- Node name is '|CPUROM:85|~144~3'
-- Equation name is '_LC5_A23', type is buried
-- synthesized logic cell
!_LC5_A23 = _LC5_A23~NOT;
_LC5_A23~NOT = LCELL( _EQ014);
_EQ014 = _LC3_A17
# A4;
-- Node name is '|CPUROM:85|:144'
-- Equation name is '_LC7_A23', type is buried
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ015);
_EQ015 = _LC3_A17
# A4;
-- Node name is '|CPUROM:85|:150'
-- Equation name is '_LC7_A15', type is buried
!_LC7_A15 = _LC7_A15~NOT;
_LC7_A15~NOT = LCELL( _EQ016);
_EQ016 = A2
# !A1
# !_LC6_A13
# A3;
-- Node name is '|CPUROM:85|~156~1'
-- Equation name is '_LC1_A21', type is buried
-- synthesized logic cell
_LC1_A21 = LCELL( _EQ017);
_EQ017 = !A4
# A0
# !A2;
-- Node name is '|CPUROM:85|~168~1'
-- Equation name is '_LC8_A22', type is buried
-- synthesized logic cell
_LC8_A22 = LCELL( _EQ018);
_EQ018 = _LC1_A21
# !A1;
-- Node name is '|CPUROM:85|:180'
-- Equation name is '_LC2_A14', type is buried
!_LC2_A14 = _LC2_A14~NOT;
_LC2_A14~NOT = LCELL( _EQ019);
_EQ019 = !_LC4_A15
# !A1
# !A3;
-- Node name is '|CPUROM:85|~192~1'
-- Equation name is '_LC6_A13', type is buried
-- synthesized logic cell
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ020);
_EQ020 = !A4
# !A0;
-- Node name is '|CPUROM:85|~192~2'
-- Equation name is '_LC2_A15', type is buried
-- synthesized logic cell
!_LC2_A15 = _LC2_A15~NOT;
_LC2_A15~NOT = LCELL( _EQ021);
_EQ021 = A2
# A1
# !A3;
-- Node name is '|CPUROM:85|:192'
-- Equation name is '_LC2_A13', type is buried
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ022);
_EQ022 = !_LC6_A13
# !_LC2_A15;
-- Node name is '|CPUROM:85|~198~1'
-- Equation name is '_LC4_A15', type is buried
-- synthesized logic cell
!_LC4_A15 = _LC4_A15~NOT;
_LC4_A15~NOT = LCELL( _EQ023);
_EQ023 = !_LC6_A13
# !A2;
-- Node name is '|CPUROM:85|:198'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ024);
_EQ024 = !A1 & A3 & _LC4_A15;
-- Node name is '|CPUROM:85|:456'
-- Equation name is '_LC5_A24', type is buried
!_LC5_A24 = _LC5_A24~NOT;
_LC5_A24~NOT = LCELL( _EQ025);
_EQ025 = !_LC1_A20 & _LC2_A23
# !_LC1_A20 & !_LC2_A13 & !_LC4_A17;
-- Node name is '|CPUROM:85|~458~1'
-- Equation name is '_LC2_A23', type is buried
-- synthesized logic cell
_LC2_A23 = LCELL( _EQ026);
_EQ026 = _LC6_A23
# _LC4_A13;
-- Node name is '|CPUROM:85|:467'
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