📄 alu8.rpt
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- 8 - C 03 OR2 0 3 0 2 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry12
- 1 - B 09 OR2 s 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~1
- 1 - B 01 AND2 s 0 3 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~2
- 1 - B 04 OR2 s 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~3
- 1 - B 10 AND2 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:139
- 4 - B 05 OR2 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:221
- 6 - B 05 OR2 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:222
- 4 - C 01 OR2 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:223
- 1 - C 03 OR2 0 3 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:224
- 5 - C 03 OR2 0 3 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:225
- 7 - C 16 OR2 0 3 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:226
- 4 - C 17 OR2 s 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~1
- 2 - C 17 OR2 s 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~2
- 4 - C 16 OR2 0 4 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:227
- 5 - B 02 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node3_3
- 4 - C 10 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node3_4
- 2 - C 12 AND2 0 2 0 1 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node4_3
- 7 - C 12 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node6_2
- 1 - C 20 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node6_3
- 3 - C 10 AND2 0 2 0 2 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node6_4
- 5 - C 10 AND2 0 2 0 2 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node6_5
- 1 - B 06 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node7_0
- 6 - C 12 AND2 0 2 0 3 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node7_1
- 5 - C 07 AND2 0 2 0 2 |alu:1|LPM_MULT:4|multcore:mult_core|decoder_node7_5
- 5 - A 06 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:94|result_node
- 3 - A 06 OR2 s 1 2 0 1 |alu:1|LPM_MUX:3|muxlut:94|~46~1
- 3 - A 09 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:112|:46
- 4 - A 09 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:112|:51
- 4 - A 11 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:130|:46
- 6 - A 11 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:130|:51
- 3 - C 13 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:148|:46
- 6 - C 13 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:148|:51
- 4 - C 08 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:166|:46
- 5 - C 08 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:166|:51
- 3 - C 06 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:184|:46
- 5 - C 06 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:184|:51
- 6 - A 04 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:202|:46
- 2 - C 16 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:202|:51
- 3 - C 16 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:220|:46
- 5 - C 16 OR2 2 2 0 1 |alu:1|LPM_MUX:3|muxlut:220|:51
- 6 - C 24 DFFE + 0 2 1 3 |cdu16:11|74161:7|f74161:sub|QA (|cdu16:11|74161:7|f74161:sub|:9)
- 2 - C 24 DFFE + 0 3 1 2 |cdu16:11|74161:7|f74161:sub|QB (|cdu16:11|74161:7|f74161:sub|:87)
- 7 - C 24 AND2 0 4 0 2 |cdu16:11|74161:7|f74161:sub|:96
- 3 - C 24 DFFE + 0 1 1 2 |cdu16:11|74161:7|f74161:sub|QC (|cdu16:11|74161:7|f74161:sub|:99)
- 5 - C 24 DFFE + 0 2 1 1 |cdu16:11|74161:7|f74161:sub|QD (|cdu16:11|74161:7|f74161:sub|:110)
- 7 - C 15 DFFE + 1 0 1 4 |cdu16:12|74161:7|f74161:sub|QA (|cdu16:12|74161:7|f74161:sub|:9)
- 2 - C 15 DFFE + 1 1 1 3 |cdu16:12|74161:7|f74161:sub|QB (|cdu16:12|74161:7|f74161:sub|:87)
- 4 - C 15 AND2 1 3 0 4 |cdu16:12|74161:7|f74161:sub|:94
- 1 - C 15 DFFE + 1 2 1 2 |cdu16:12|74161:7|f74161:sub|QC (|cdu16:12|74161:7|f74161:sub|:99)
- 1 - C 24 DFFE + 1 1 1 4 |cdu16:12|74161:7|f74161:sub|QD (|cdu16:12|74161:7|f74161:sub|:110)
- 5 - A 01 AND2 2 0 0 8 :42
- 2 - A 01 AND2 2 0 0 8 :43
- 4 - A 05 AND2 2 0 0 8 :44
- 8 - A 05 AND2 2 0 0 8 :45
- 2 - A 05 AND2 2 0 0 8 :46
- 1 - A 05 AND2 2 0 0 8 :47
- 2 - A 10 OR2 s 2 2 0 1 |74244:54|~1~1~3~2
- 1 - A 06 OR2 s 1 2 0 1 |74244:54|~1~1~3~3
- 2 - A 06 OR2 s 2 2 0 1 |74244:54|~1~1~3~4
- 8 - A 06 OR2 1 3 1 0 |74244:54|~1~1~3
- 4 - A 03 OR2 s 2 2 0 1 |74244:54|~6~1~3~2
- 1 - A 09 OR2 s 2 2 0 1 |74244:54|~6~1~3~3
- 2 - A 09 OR2 s 1 3 0 1 |74244:54|~6~1~3~4
- 7 - A 09 OR2 1 3 1 0 |74244:54|~6~1~3
- 1 - A 10 OR2 s 2 2 0 1 |74244:54|~10~1~3~2
- 1 - A 11 OR2 s 2 2 0 1 |74244:54|~10~1~3~3
- 2 - A 11 OR2 s 1 3 0 1 |74244:54|~10~1~3~4
- 3 - A 11 OR2 1 3 1 0 |74244:54|~10~1~3
- 4 - A 15 OR2 s 2 2 0 1 |74244:54|~11~1~3~2
- 1 - C 13 OR2 s 2 2 0 1 |74244:54|~11~1~3~3
- 2 - C 13 OR2 s 1 3 0 1 |74244:54|~11~1~3~4
- 5 - C 13 OR2 1 3 1 0 |74244:54|~11~1~3
- 1 - A 15 OR2 s 2 2 0 1 |74244:54|~26~1~3~2
- 8 - C 24 OR2 s 2 2 0 1 |74244:54|~26~1~3~3
- 1 - C 16 OR2 s 1 3 0 1 |74244:54|~26~1~3~4
- 6 - C 16 OR2 1 3 1 0 |74244:54|~26~1~3
- 7 - A 03 OR2 s 2 2 0 1 |74244:54|~27~1~3~2
- 3 - A 04 OR2 s 2 2 0 1 |74244:54|~27~1~3~3
- 5 - A 04 OR2 s 1 3 0 1 |74244:54|~27~1~3~4
- 1 - A 04 OR2 1 3 1 0 |74244:54|~27~1~3
- 2 - A 04 OR2 s 3 0 0 1 |74244:54|~31~1~2~2
- 4 - A 04 OR2 3 1 0 0 |74244:54|~31~1~2
- 8 - A 03 OR2 s 2 2 0 1 |74244:54|~31~1~3~2
- 1 - C 06 OR2 s 2 2 0 1 |74244:54|~31~1~3~3
- 2 - C 06 OR2 s 1 3 0 1 |74244:54|~31~1~3~4
- 8 - C 06 OR2 1 3 1 0 |74244:54|~31~1~3
- 4 - A 10 OR2 s 2 2 0 1 |74244:54|~36~1~3~2
- 2 - C 08 OR2 s 2 2 0 1 |74244:54|~36~1~3~3
- 3 - C 08 OR2 s 1 3 0 1 |74244:54|~36~1~3~4
- 1 - C 08 OR2 1 3 1 0 |74244:54|~36~1~3
- 1 - A 12 DFFE 0 2 0 14 |74273:52|Q8 (|74273:52|:12)
- 7 - A 01 DFFE 0 2 0 17 |74273:52|Q7 (|74273:52|:13)
- 2 - A 12 DFFE 0 2 0 23 |74273:52|Q6 (|74273:52|:14)
- 7 - A 12 DFFE 0 2 0 25 |74273:52|Q5 (|74273:52|:15)
- 6 - A 01 DFFE 0 2 0 19 |74273:52|Q4 (|74273:52|:16)
- 2 - A 08 DFFE 0 2 0 23 |74273:52|Q3 (|74273:52|:17)
- 2 - A 07 DFFE 0 2 0 24 |74273:52|Q2 (|74273:52|:18)
- 3 - A 01 DFFE 0 2 0 17 |74273:52|Q1 (|74273:52|:19)
- 4 - A 12 DFFE 0 2 0 19 |74273:53|Q8 (|74273:53|:12)
- 8 - A 01 DFFE 0 2 0 22 |74273:53|Q7 (|74273:53|:13)
- 5 - A 12 DFFE 0 2 0 21 |74273:53|Q6 (|74273:53|:14)
- 8 - A 12 DFFE 0 2 0 21 |74273:53|Q5 (|74273:53|:15)
- 4 - A 01 DFFE 0 2 0 21 |74273:53|Q4 (|74273:53|:16)
- 3 - A 12 DFFE 0 2 0 21 |74273:53|Q3 (|74273:53|:17)
- 6 - A 12 DFFE 0 2 0 20 |74273:53|Q2 (|74273:53|:18)
- 1 - A 01 DFFE 0 2 0 17 |74273:53|Q1 (|74273:53|:19)
- 7 - A 06 DFFE 0 2 0 1 |74374:48|:13
- 5 - A 09 DFFE 0 2 0 1 |74374:48|:14
- 7 - A 11 DFFE 0 2 0 1 |74374:48|:15
- 7 - C 13 DFFE 0 2 0 1 |74374:48|:16
- 6 - C 08 DFFE 0 2 0 1 |74374:48|:17
- 6 - C 06 DFFE 0 2 0 1 |74374:48|:18
- 7 - A 04 DFFE 0 2 0 1 |74374:48|:19
- 4 - C 24 DFFE 0 2 0 1 |74374:48|:20
- 6 - A 10 DFFE 0 2 0 1 |74374:49|:13
- 1 - A 03 DFFE 0 2 0 1 |74374:49|:14
- 3 - A 10 DFFE 0 2 0 1 |74374:49|:15
- 3 - A 15 DFFE 0 2 0 1 |74374:49|:16
- 8 - A 10 DFFE 0 2 0 1 |74374:49|:17
- 6 - A 03 DFFE 0 2 0 1 |74374:49|:18
- 3 - A 03 DFFE 0 2 0 1 |74374:49|:19
- 6 - A 15 DFFE 0 2 0 1 |74374:49|:20
- 5 - A 10 DFFE 0 2 0 1 |74374:50|:13
- 1 - A 07 DFFE 0 2 0 1 |74374:50|:14
- 1 - A 08 DFFE 0 2 0 1 |74374:50|:15
- 2 - A 15 DFFE 0 2 0 1 |74374:50|:16
- 7 - A 10 DFFE 0 2 0 1 |74374:50|:17
- 5 - A 03 DFFE 0 2 0 1 |74374:50|:18
- 2 - A 03 DFFE 0 2 0 1 |74374:50|:19
- 5 - A 15 DFFE 0 2 0 1 |74374:50|:20
- 6 - A 06 DFFE 0 2 0 1 |74374:51|:13
- 6 - A 09 DFFE 0 2 0 1 |74374:51|:14
- 8 - A 11 DFFE 0 2 0 1 |74374:51|:15
- 8 - C 13 DFFE 0 2 0 1 |74374:51|:16
- 7 - C 08 DFFE 0 2 0 1 |74374:51|:17
- 7 - C 06 DFFE 0 2 0 1 |74374:51|:18
- 8 - A 04 DFFE 0 2 0 1 |74374:51|:19
- 8 - C 16 DFFE 0 2 0 1 |74374:51|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\alu8.rpt
alu8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 32/ 96( 33%) 22/ 48( 45%) 0/ 48( 0%) 6/16( 37%) 0/16( 0%) 3/16( 18%)
B: 20/ 96( 20%) 32/ 48( 66%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 46/ 96( 47%) 27/ 48( 56%) 8/ 48( 16%) 1/16( 6%) 5/16( 31%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 1/4( 25%) 0/4( 0%) 1/4( 25%)
04: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
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