📄 or.rpt
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Project Informationc:\documents and settings\user\cpu_design\cpu_module\or.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 09/12/2007 16:58:14
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
or EPM7032LC44-6 16 8 0 8 0 25 %
User Pins: 16 8 0
Project Informationc:\documents and settings\user\cpu_design\cpu_module\or.rpt
** FILE HIERARCHY **
|lpm_or:1|
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
***** Logic for device 'or' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
a a a
1 1 0 V G G G G G
_ _ _ C N N N N N r r
6 7 0 C D D D D D 7 6
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
a1_5 | 7 39 | r5
a1_4 | 8 38 | r4
a1_3 | 9 37 | r3
GND | 10 36 | r1
a1_2 | 11 35 | VCC
a1_1 | 12 EPM7032LC44-6 34 | r2
a1_0 | 13 33 | r0
a0_7 | 14 32 | RESERVED
VCC | 15 31 | RESERVED
a0_1 | 16 30 | GND
a0_2 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
a a a a G V R R R R R
0 0 0 0 N C E E E E E
_ _ _ _ D C S S S S S
3 4 5 6 E E E E E
R R R R R
V V V V V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 8/16( 50%) 0/16( 0%) 16/36( 44%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 24/32 ( 75%)
Total logic cells used: 8/32 ( 25%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 8/32 ( 25%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 2.00
Total fan-in: 16
Total input pins required: 16
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 8
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 1 0 a0_0
16 (11) (A) INPUT 0 0 0 0 0 1 0 a0_1
17 (12) (A) INPUT 0 0 0 0 0 1 0 a0_2
18 (13) (A) INPUT 0 0 0 0 0 1 0 a0_3
19 (14) (A) INPUT 0 0 0 0 0 1 0 a0_4
20 (15) (A) INPUT 0 0 0 0 0 1 0 a0_5
21 (16) (A) INPUT 0 0 0 0 0 1 0 a0_6
14 (10) (A) INPUT 0 0 0 0 0 1 0 a0_7
13 (9) (A) INPUT 0 0 0 0 0 1 0 a1_0
12 (8) (A) INPUT 0 0 0 0 0 1 0 a1_1
11 (7) (A) INPUT 0 0 0 0 0 1 0 a1_2
9 (6) (A) INPUT 0 0 0 0 0 1 0 a1_3
8 (5) (A) INPUT 0 0 0 0 0 1 0 a1_4
7 (4) (A) INPUT 0 0 0 0 0 1 0 a1_5
6 (3) (A) INPUT 0 0 0 0 0 1 0 a1_6
5 (2) (A) INPUT 0 0 0 0 0 1 0 a1_7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 24 B OUTPUT t 0 0 0 2 0 0 0 r0
36 22 B OUTPUT t 0 0 0 2 0 0 0 r1
34 23 B OUTPUT t 0 0 0 2 0 0 0 r2
37 21 B OUTPUT t 0 0 0 2 0 0 0 r3
38 20 B OUTPUT t 0 0 0 2 0 0 0 r4
39 19 B OUTPUT t 0 0 0 2 0 0 0 r5
40 18 B OUTPUT t 0 0 0 2 0 0 0 r6
41 17 B OUTPUT t 0 0 0 2 0 0 0 r7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC24 r0
| +------------- LC22 r1
| | +----------- LC23 r2
| | | +--------- LC21 r3
| | | | +------- LC20 r4
| | | | | +----- LC19 r5
| | | | | | +--- LC18 r6
| | | | | | | +- LC17 r7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'B'
LC | | | | | | | | | A B | Logic cells that feed LAB 'B':
Pin
4 -> * - - - - - - - | - * | <-- a0_0
16 -> - * - - - - - - | - * | <-- a0_1
17 -> - - * - - - - - | - * | <-- a0_2
18 -> - - - * - - - - | - * | <-- a0_3
19 -> - - - - * - - - | - * | <-- a0_4
20 -> - - - - - * - - | - * | <-- a0_5
21 -> - - - - - - * - | - * | <-- a0_6
14 -> - - - - - - - * | - * | <-- a0_7
13 -> * - - - - - - - | - * | <-- a1_0
12 -> - * - - - - - - | - * | <-- a1_1
11 -> - - * - - - - - | - * | <-- a1_2
9 -> - - - * - - - - | - * | <-- a1_3
8 -> - - - - * - - - | - * | <-- a1_4
7 -> - - - - - * - - | - * | <-- a1_5
6 -> - - - - - - * - | - * | <-- a1_6
5 -> - - - - - - - * | - * | <-- a1_7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\or.rpt
or
** EQUATIONS **
a0_0 : INPUT;
a0_1 : INPUT;
a0_2 : INPUT;
a0_3 : INPUT;
a0_4 : INPUT;
a0_5 : INPUT;
a0_6 : INPUT;
a0_7 : INPUT;
a1_0 : INPUT;
a1_1 : INPUT;
a1_2 : INPUT;
a1_3 : INPUT;
a1_4 : INPUT;
a1_5 : INPUT;
a1_6 : INPUT;
a1_7 : INPUT;
-- Node name is 'r0'
-- Equation name is 'r0', location is LC024, type is output.
r0 = LCELL( _EQ001 $ VCC);
_EQ001 = !a0_0 & !a1_0;
-- Node name is 'r1'
-- Equation name is 'r1', location is LC022, type is output.
r1 = LCELL( _EQ002 $ VCC);
_EQ002 = !a0_1 & !a1_1;
-- Node name is 'r2'
-- Equation name is 'r2', location is LC023, type is output.
r2 = LCELL( _EQ003 $ VCC);
_EQ003 = !a0_2 & !a1_2;
-- Node name is 'r3'
-- Equation name is 'r3', location is LC021, type is output.
r3 = LCELL( _EQ004 $ VCC);
_EQ004 = !a0_3 & !a1_3;
-- Node name is 'r4'
-- Equation name is 'r4', location is LC020, type is output.
r4 = LCELL( _EQ005 $ VCC);
_EQ005 = !a0_4 & !a1_4;
-- Node name is 'r5'
-- Equation name is 'r5', location is LC019, type is output.
r5 = LCELL( _EQ006 $ VCC);
_EQ006 = !a0_5 & !a1_5;
-- Node name is 'r6'
-- Equation name is 'r6', location is LC018, type is output.
r6 = LCELL( _EQ007 $ VCC);
_EQ007 = !a0_6 & !a1_6;
-- Node name is 'r7'
-- Equation name is 'r7', location is LC017, type is output.
r7 = LCELL( _EQ008 $ VCC);
_EQ008 = !a0_7 & !a1_7;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informationc:\documents and settings\user\cpu_design\cpu_module\or.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,988K
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