📄 alureg.rpt
字号:
C18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 3/22( 13%)
C19 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
C20 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
C23 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
C24 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 43/53 ( 81%)
Total logic cells used: 361/576 ( 62%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.07/4 ( 76%)
Total fan-in: 1109/2304 ( 48%)
Total input pins required: 28
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 361
Total flipflops required: 69
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 95/ 576 ( 16%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 5 8 8 8 6 8 8 8 8 6 8 0 1 0 7 6 8 8 8 1 0 0 4 8 140/0
B: 0 8 0 0 7 0 8 0 0 8 7 8 0 8 8 6 8 0 8 8 0 8 0 0 0 100/0
C: 6 0 7 4 0 8 8 4 8 5 4 8 0 8 8 0 4 8 8 7 7 0 0 6 3 121/0
Total: 14 13 15 12 15 14 24 12 16 21 17 24 0 17 16 13 18 16 24 23 8 8 0 10 11 361/0
Device-Specific Information: e:\cpu_design\cpumodel\alureg.rpt
alureg
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
3 - - - 12 INPUT 0 0 0 9 ALU_BUS
1 - - - -- INPUT G 0 0 0 2 CLKJP
51 - - - 18 INPUT 0 0 0 1 DP
28 - - C -- BIDIR 0 1 0 4 D0
64 - - B -- BIDIR 0 1 0 4 D1
67 - - B -- BIDIR 0 1 0 4 D2
17 - - A -- BIDIR 0 1 0 4 D3
19 - - A -- BIDIR 0 1 0 4 D4
18 - - A -- BIDIR 0 1 0 4 D5
27 - - C -- BIDIR 0 1 0 4 D6
7 - - - 03 BIDIR 0 1 0 4 D7
11 - - - 01 INPUT 0 0 0 1 in0
65 - - B -- INPUT 0 0 0 1 in1
22 - - B -- INPUT 0 0 0 1 in2
71 - - A -- INPUT 0 0 0 1 in3
35 - - - 06 INPUT 0 0 0 1 in4
38 - - - 10 INPUT 0 0 0 1 in5
37 - - - 09 INPUT 0 0 0 1 in6
73 - - A -- INPUT 0 0 0 1 in7
72 - - A -- INPUT 0 0 0 1 LDDR1
83 - - - 13 INPUT 0 0 0 1 LDDR2
81 - - - 22 INPUT 0 0 0 1 LDR0
52 - - - 19 INPUT 0 0 0 1 LDR1
79 - - - 24 INPUT 0 0 0 1 LDR2
53 - - - 20 INPUT 0 0 0 1 LDR3
80 - - - 23 INPUT 0 0 0 1 QD
23 - - B -- INPUT 0 0 0 9 r_bus
42 - - - -- INPUT 0 0 0 16 sa0
6 - - - 04 INPUT 0 0 0 8 sa1
44 - - - -- INPUT 0 0 0 16 sb0
5 - - - 05 INPUT 0 0 0 8 sb1
21 - - B -- INPUT 0 0 0 9 SW_BUS
43 - - - -- INPUT 0 0 0 16 s0
84 - - - -- INPUT 0 0 0 16 s1
9 - - - 02 INPUT 0 0 0 9 s2
2 - - - -- INPUT G 0 0 0 2 tj
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cpu_design\cpumodel\alureg.rpt
alureg
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
16 - - A -- OUTPUT 0 1 0 0 CN4
28 - - C -- TRI 0 1 0 4 D0
64 - - B -- TRI 0 1 0 4 D1
67 - - B -- TRI 0 1 0 4 D2
17 - - A -- TRI 0 1 0 4 D3
19 - - A -- TRI 0 1 0 4 D4
18 - - A -- TRI 0 1 0 4 D5
27 - - C -- TRI 0 1 0 4 D6
7 - - - 03 TRI 0 1 0 4 D7
61 - - C -- OUTPUT 0 1 0 0 R0_0
58 - - C -- OUTPUT 0 1 0 0 R0_1
60 - - C -- OUTPUT 0 1 0 0 R0_2
50 - - - 17 OUTPUT 0 1 0 0 R0_3
36 - - - 07 OUTPUT 0 1 0 0 R0_4
62 - - C -- OUTPUT 0 1 0 0 R0_5
29 - - C -- OUTPUT 0 1 0 0 R0_6
59 - - C -- OUTPUT 0 1 0 0 R0_7
30 - - C -- OUTPUT 0 1 0 0 t1
70 - - A -- OUTPUT 0 1 0 0 t2
66 - - B -- OUTPUT 0 1 0 0 t3
78 - - - 24 OUTPUT 0 1 0 0 t4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
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