📄 alureg.rpt
字号:
Device-Specific Information: e:\cpu_design\cpumodel\alureg.rpt
alureg
***** Logic for device 'alureg' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: e:\cpu_design\cpumodel\alureg.rpt
alureg
** ERROR SUMMARY **
Info: Chip 'alureg' in device 'EPF10K10LC84-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R R O
E E A N
S S V L G F
E E C U C L N _ ^
R R C _ L D D L L # D n
i V V s s I B K D I D D T O C
n E s E D a b N U t J s R N R Q R t C N E
0 D 2 D 7 1 1 T S j P 1 2 T 0 D 2 4 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | in7
^nCE | 14 72 | LDDR1
#TDI | 15 71 | in3
CN4 | 16 70 | t2
D3 | 17 69 | RESERVED
D5 | 18 68 | GNDINT
D4 | 19 67 | D2
VCCINT | 20 66 | t3
SW_BUS | 21 65 | in1
in2 | 22 EPF10K10LC84-3 64 | D1
r_bus | 23 63 | VCCINT
RESERVED | 24 62 | R0_5
RESERVED | 25 61 | R0_0
GNDINT | 26 60 | R0_2
D6 | 27 59 | R0_7
D0 | 28 58 | R0_1
R0_6 | 29 57 | #TMS
t1 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ i R i i R V G s s s V G R R R R D L L
C n n 0 n n E C N a 0 b C N E E E 0 P D D
C C 4 _ 6 5 S C D 0 0 C D S S S _ R R
I O 4 E I I I I E E E 3 1 3
N N R N N N N R R R
T F V T T T T V V V
I E E E E
G D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\cpu_design\cpumodel\alureg.rpt
alureg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
A2 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A3 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
A4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
A5 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A6 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A10 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 8/22( 36%)
A11 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A15 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
A16 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
A17 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A23 4/ 8( 50%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
B2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B5 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
B7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
B10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
B11 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B14 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
B15 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 14/22( 63%)
B16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
B19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
B21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
C1 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 15/22( 68%)
C3 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
C4 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 5/22( 22%)
C6 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 0/2 12/22( 54%)
C7 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
C8 4/ 8( 50%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 5/22( 22%)
C9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
C10 5/ 8( 62%) 4/ 8( 50%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
C11 4/ 8( 50%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 8/22( 36%)
C12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 16/22( 72%)
C13 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
C14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 6/22( 27%)
C16 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
C17 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 0/2 8/22( 36%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -