📄 shutong.rpt
字号:
A5 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A6 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A7 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
A8 2/ 8( 25%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B1 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
B2 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
B3 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
B4 6/ 8( 75%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
B6 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
B7 8/ 8(100%) 5/ 8( 62%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
B8 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
B9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 18/22( 81%)
B10 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 10/22( 45%)
B11 4/ 8( 50%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
B12 4/ 8( 50%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
B13 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
B15 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
B16 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 2/2 0/2 7/22( 31%)
B17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 16/22( 72%)
B18 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 11/22( 50%)
B19 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
B20 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 6/22( 27%)
B21 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 0/2 8/22( 36%)
B22 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 11/22( 50%)
B23 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
B24 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
C1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
C2 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
C3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
C4 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
C5 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C6 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
C7 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
C8 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 10/22( 45%)
C9 5/ 8( 62%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
C10 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C11 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
C12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
C15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
C17 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
C18 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
C19 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
C20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C22 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
C23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
C24 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
B25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 1/2 2/2 17/22( 77%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 55/96 ( 57%)
Total logic cells used: 384/576 ( 66%)
Total embedded cells used: 8/24 ( 33%)
Total EABs used: 1/3 ( 33%)
Average fan-in: 3.09/4 ( 77%)
Total fan-in: 1190/2304 ( 51%)
Total input pins required: 36
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 384
Total flipflops required: 80
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 110/ 576 ( 19%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 8 8 8 5 2 0 0 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 64/0
B: 7 8 8 6 8 7 8 8 8 4 4 4 8 7 0 8 8 8 7 4 8 8 8 7 7 160/8
C: 8 7 8 8 7 8 8 8 5 2 8 8 0 0 8 8 8 3 8 8 1 8 7 8 8 160/0
Total: 23 23 24 22 23 23 21 18 13 6 20 12 8 8 8 16 16 11 15 12 9 16 15 15 15 384/8
Device-Specific Information: e:\cpu_design\cpumodel\shutong.rpt
shutong
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - C -- INPUT 0 0 0 9 alu_bus
19 - - B -- BIDIR 0 1 0 7 D0
91 - - B -- BIDIR 0 1 0 7 D1
90 - - B -- BIDIR 0 1 0 7 D2
92 - - B -- BIDIR 0 1 0 7 D3
88 - - B -- BIDIR 0 1 0 7 D4
27 - - C -- BIDIR 0 1 0 7 D5
23 - - B -- BIDIR 0 1 0 7 D6
22 - - B -- BIDIR 0 1 0 7 D7
10 - - A -- INPUT 0 0 0 1 in
133 - - - 17 INPUT 0 0 0 1 in0
60 - - - 12 INPUT 0 0 0 1 in1
122 - - - 12 INPUT 0 0 0 1 in2
59 - - - 12 INPUT 0 0 0 1 in3
117 - - - 06 INPUT 0 0 0 1 in4
132 - - - 16 INPUT 0 0 0 1 in5
136 - - - 19 INPUT 0 0 0 1 in6
44 - - - 18 INPUT 0 0 0 1 in7
11 - - A -- INPUT 0 0 0 1 ldar
114 - - - 04 INPUT 0 0 0 1 lddr1
113 - - - 03 INPUT 0 0 0 1 lddr2
37 - - - 23 INPUT 0 0 0 1 ldr0
36 - - - 24 INPUT 0 0 0 1 ldr1
137 - - - 19 INPUT 0 0 0 1 ldr2
130 - - - 14 INPUT 0 0 0 1 ldr3
39 - - - 21 INPUT 0 0 0 2 out
131 - - - 15 INPUT 0 0 0 9 pc_bus
41 - - - 20 INPUT 0 0 0 2 r_bus
143 - - - 24 INPUT 0 0 0 10 rd
126 - - - -- INPUT 0 0 0 16 sel_dr10
42 - - - 19 INPUT 0 0 0 8 sel_dr11
124 - - - -- INPUT 0 0 0 16 sel_dr20
18 - - B -- INPUT 0 0 0 8 sel_dr21
101 - - A -- INPUT 0 0 0 1 sw_bus
56 - - - -- INPUT 0 0 0 20 s0
125 - - - -- INPUT 0 0 0 11 s1
82 - - C -- INPUT 0 0 0 12 s2
55 - - - -- INPUT G 0 0 0 2 t1
99 - - A -- INPUT 0 0 0 2 t2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -