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📄 shutong.rpt

📁 简单的CPU设计数字系统实验
💻 RPT
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|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder1|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:result_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:carry_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:oflow_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_mult:4|altshift:external_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:5|
|alu_reg:101|alu:142|lpm_add_sub:5|addcore:adder|
|alu_reg:101|alu:142|lpm_add_sub:5|altshift:result_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:5|altshift:carry_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:5|altshift:oflow_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:44|
|alu_reg:101|alu:142|lpm_add_sub:44|addcore:adder|
|alu_reg:101|alu:142|lpm_add_sub:44|altshift:result_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:44|altshift:carry_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_add_sub:44|altshift:oflow_ext_latency_ffs|
|alu_reg:101|alu:142|lpm_clshift:39|
|alu_reg:101|alu:142|mux:52|
|alu_reg:101|alu:142|mux:52|lpm_mux:31|
|alu_reg:101|alu:142|mux:52|lpm_mux:31|altshift:external_latency_ffs|
|alu_reg:101|alu:142|mux:52|lpm_mux:31|muxlut:42|


Device-Specific Information:                e:\cpu_design\cpumodel\shutong.rpt
shutong

***** Logic for device 'shutong' compiled without errors.




Device: EPF10K10TC144-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                                                                                         
                                                                                         
                R     R     R     R             R   s   s       R       R       R   R    
                E     E     E     E             E   e   e       E       E       E   E    
                S     S     S     S       p     S G l   l V     S       S       S   S    
                E     E   G E     E V     c   G E N _   _ C     E       E V l l E   E    
                R     R   N R l   R C     _ l N R D d   d C     R A A   R C d d R   R    
                V     V   D V d i V C i i b d D V I r   r I i   V D D i V C d d V   V    
                E r t E r I E r n E I n n u r I E N 1 s 2 N n w E R R n E I r r E r E r  
                D d 3 D 2 O D 2 6 D O 0 5 s 3 O D T 0 1 0 T 2 e D 7 0 4 D O 1 2 D 3 D 4  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GNDIO 
    VCCINT |  6                                                                         103 | GNDINT 
  RESERVED |  7                                                                         102 | RESERVED 
  RESERVED |  8                                                                         101 | sw_bus 
  RESERVED |  9                                                                         100 | RESERVED 
        in | 10                                                                          99 | t2 
      ldar | 11                                                                          98 | RESERVED 
  RESERVED | 12                                                                          97 | ADR2 
  RESERVED | 13                                                                          96 | 161pc 
  RESERVED | 14                                                                          95 | RESERVED 
     GNDIO | 15                                                                          94 | VCCIO 
    GNDINT | 16                                                                          93 | VCCINT 
        r0 | 17                                                                          92 | D3 
  sel_dr21 | 18                                                                          91 | D1 
        D0 | 19                             EPF10K10TC144-3                              90 | D2 
        r7 | 20                                                                          89 | ADR6 
        r5 | 21                                                                          88 | D4 
        D7 | 22                                                                          87 | ADR5 
        D6 | 23                                                                          86 | ADR3 
     VCCIO | 24                                                                          85 | GNDIO 
    VCCINT | 25                                                                          84 | GNDINT 
  RESERVED | 26                                                                          83 | RESERVED 
        D5 | 27                                                                          82 | s2 
   alu_bus | 28                                                                          81 | RESERVED 
  RESERVED | 29                                                                          80 | RESERVED 
      cout | 30                                                                          79 | RESERVED 
  RESERVED | 31                                                                          78 | RESERVED 
  RESERVED | 32                                                                          77 | ^MSEL0 
  RESERVED | 33                                                                          76 | ^MSEL1 
      #TMS | 34                                                                          75 | VCCINT 
  ^nSTATUS | 35                                                                          74 | ^nCONFIG 
      ldr1 | 36                                                                          73 | r1 
           |      38  40  42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  _| 
            \   37  39  41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71   | 
             \--------------------------------------------------------------------------- 
                l R o G r s R i V R R r R G R V V 1 t s G G i i V R R R 1 G A A R R V R  
                d E u N _ e E n C E E 6 E N E C C 6 1 0 N N n n C E E E 6 N D D E E C E  
                r S t D b l S 7 C S S   S D S C C 1     D D 3 1 C S S S 1 D R R S S C S  
                0 E   I u _ E   I E E   E I E I I c     I I     I E E E l I 4 1 E E I E  
                  R   O s d R   O R R   R O R N N l     N N     O R R R o O     R R O R  
                  V       r V     V V   V   V T T r     T T       V V V a       V V   V  
                  E       1 E     E E   E   E     n               E E E d       E E   E  
                  D       1 D     D D   D   D                     D D D         D D   D  
                                                                                         
                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                e:\cpu_design\cpumodel\shutong.rpt
shutong

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    0/2    0/2       6/22( 27%)   
A2       8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    0/2    0/2      10/22( 45%)   
A3       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       8/22( 36%)   
A4       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2      13/22( 59%)   

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