📄 test_ram.rpt
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-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ007);
_EQ007 = _EC3_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC3_B & _LC3_B12
# _LC3_B12 & !_LC5_B7;
-- Node name is '|LPM_RAM_IO:81|datatri7~1~2'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ008);
_EQ008 = !pc_bus
# _LC5_B7;
-- Node name is '|LPM_RAM_IO:81|datatri7~1~3'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ009);
_EQ009 = _EC1_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC1_B & _LC1_B12
# _LC1_B12 & !_LC5_B7;
-- Node name is '|LPM_RAM_IO:81|:92' from file "lpm_ram_io.tdf" line 187, column 27
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ010);
_EQ010 = memenab & !rd & we;
-- Node name is '|LPM_RAM_IO:81|:93' from file "lpm_ram_io.tdf" line 198, column 25
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ011);
_EQ011 = memenab & rd;
-- Node name is '|74161:74|f74161:sub|:9' = '|74161:74|f74161:sub|QA'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = DFFE( _EQ012, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ012 = d4 & !161oad
# !_LC5_B3 & _LC6_B12 & 161oad
# _LC5_B3 & !_LC6_B12 & 161oad;
-- Node name is '|74161:74|f74161:sub|:87' = '|74161:74|f74161:sub|QB'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = DFFE( _EQ013, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ013 = d5 & !161oad
# !_LC2_B12 & _LC5_B12 & 161oad
# _LC2_B12 & !_LC5_B12 & 161oad;
-- Node name is '|74161:74|f74161:sub|:99' = '|74161:74|f74161:sub|QC'
-- Equation name is '_LC3_B12', type is buried
_LC3_B12 = DFFE( _EQ014, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ014 = d6 & !161oad
# _LC3_B12 & !_LC7_B12 & 161oad
# !_LC3_B12 & _LC7_B12 & 161oad;
-- Node name is '|74161:74|f74161:sub|:110' = '|74161:74|f74161:sub|QD'
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = DFFE( _EQ015, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ015 = d7 & !161oad
# _LC1_B12 & !_LC8_B12 & 161oad
# !_LC1_B12 & _LC8_B12 & 161oad;
-- Node name is '|74161:74|f74161:sub|:80'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ016);
_EQ016 = _LC5_B3 & _LC6_B12;
-- Node name is '|74161:74|f74161:sub|:84'
-- Equation name is '_LC7_B12', type is buried
_LC7_B12 = LCELL( _EQ017);
_EQ017 = _LC5_B3 & _LC5_B12 & _LC6_B12;
-- Node name is '|74161:74|f74161:sub|:94'
-- Equation name is '_LC8_B12', type is buried
_LC8_B12 = LCELL( _EQ018);
_EQ018 = _LC3_B12 & _LC5_B3 & _LC5_B12 & _LC6_B12;
-- Node name is '|74161:75|f74161:sub|:9' = '|74161:75|f74161:sub|QA'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = DFFE( _EQ019, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ019 = d0 & !161oad
# !_LC6_B3 & 161oad;
-- Node name is '|74161:75|f74161:sub|:87' = '|74161:75|f74161:sub|QB'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ020, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ020 = d1 & !161oad
# _LC4_B3 & !_LC6_B3 & 161oad
# !_LC4_B3 & _LC6_B3 & 161oad;
-- Node name is '|74161:75|f74161:sub|:99' = '|74161:75|f74161:sub|QC'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ021, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ021 = d2 & !161oad
# _LC3_B3 & !_LC7_B3 & 161oad
# !_LC3_B3 & _LC7_B3 & 161oad;
-- Node name is '|74161:75|f74161:sub|:110' = '|74161:75|f74161:sub|QD'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _EQ022, _LC3_B11, GLOBAL( 161clrn), VCC, VCC);
_EQ022 = d3 & !161oad
# _LC2_B3 & !_LC8_B3 & 161oad
# !_LC2_B3 & _LC8_B3 & 161oad;
-- Node name is '|74161:75|f74161:sub|:84'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ023);
_EQ023 = _LC4_B3 & _LC6_B3;
-- Node name is '|74161:75|f74161:sub|:94'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ024);
_EQ024 = _LC3_B3 & _LC4_B3 & _LC6_B3;
-- Node name is '|74161:75|f74161:sub|:104'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ025);
_EQ025 = _LC2_B3 & _LC3_B3 & _LC4_B3 & _LC6_B3;
-- Node name is '|74273:78|:19' = '|74273:78|Q1'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = DFFE( d0, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:18' = '|74273:78|Q2'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = DFFE( d1, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:17' = '|74273:78|Q3'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( d2, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:16' = '|74273:78|Q4'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = DFFE( d3, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:15' = '|74273:78|Q5'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = DFFE( d4, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:14' = '|74273:78|Q6'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = DFFE( d5, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:13' = '|74273:78|Q7'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( d6, _LC3_B2, VCC, VCC, VCC);
-- Node name is '|74273:78|:12' = '|74273:78|Q8'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( d7, _LC3_B2, VCC, VCC, VCC);
-- Node name is ':62'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ026);
_EQ026 = LDAR & t2;
-- Node name is ':63'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ027);
_EQ027 = t2 & 161pc;
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC7_B', type is memory
_EC7_B = MEMORY_SEGMENT( d0, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC2_B', type is memory
_EC2_B = MEMORY_SEGMENT( d1, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC6_B', type is memory
_EC6_B = MEMORY_SEGMENT( d2, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC5_B', type is memory
_EC5_B = MEMORY_SEGMENT( d3, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC4_B', type is memory
_EC4_B = MEMORY_SEGMENT( d4, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC8_B', type is memory
_EC8_B = MEMORY_SEGMENT( d5, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC3_B', type is memory
_EC3_B = MEMORY_SEGMENT( d6, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:81|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12
-- Equation name is '_EC1_B', type is memory
_EC1_B = MEMORY_SEGMENT( d7, GLOBAL( t1), VCC, _LC4_B7, VCC, _LC7_B2, _LC7_B4, _LC8_B2, _LC5_B2, _LC6_B2, _LC1_B2, _LC2_B2, _LC4_B2, VCC, VCC, VCC,);
Project Information c:\documents and settings\user\cpumodel\test_ram.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,103K
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