📄 test_ram.rpt
字号:
11 - - - 01 OUTPUT 0 1 0 0 adr2
18 - - A -- OUTPUT 0 1 0 0 adr3
64 - - B -- OUTPUT 0 1 0 0 adr4
27 - - C -- OUTPUT 0 1 0 0 adr5
28 - - C -- OUTPUT 0 1 0 0 adr6
9 - - - 02 OUTPUT 0 1 0 0 adr7
67 - - B -- TRI 0 1 0 3 d0
21 - - B -- TRI 0 1 0 3 d1
24 - - B -- TRI 0 1 0 3 d2
66 - - B -- TRI 0 1 0 3 d3
25 - - B -- TRI 0 1 0 3 d4
23 - - B -- TRI 0 1 0 3 d5
22 - - B -- TRI 0 1 0 3 d6
65 - - B -- TRI 0 1 0 3 d7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\documents and settings\user\cpumodel\test_ram.rpt
test_ram
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 7 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_0
- - 2 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_1
- - 6 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_2
- - 5 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_3
- - 4 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_4
- - 8 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_5
- - 3 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_6
- - 1 B -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:81|altram:sram|segment0_7
- 1 - B 03 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri0~1~3
- 1 - B 05 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri1~1~3
- 6 - B 07 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri2~1~3
- 3 - B 07 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri3~1~3
- 8 - B 07 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri4~1~3
- 4 - B 12 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri5~1~3
- 2 - B 07 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri6~1~3
- 1 - B 07 OR2 1 1 0 0 |LPM_RAM_IO:81|datatri7~1~2
- 5 - B 05 OR2 1 3 1 0 |LPM_RAM_IO:81|datatri7~1~3
- 4 - B 07 AND2 3 0 0 8 |LPM_RAM_IO:81|:92
- 5 - B 07 AND2 2 0 0 9 |LPM_RAM_IO:81|:93
- 3 - B 02 AND2 2 0 0 8 :62
- 3 - B 11 AND2 2 0 0 8 :63
- 6 - B 12 DFFE 1 3 0 4 |74161:74|f74161:sub|QA (|74161:74|f74161:sub|:9)
- 2 - B 12 AND2 0 2 0 1 |74161:74|f74161:sub|:80
- 7 - B 12 AND2 0 3 0 1 |74161:74|f74161:sub|:84
- 5 - B 12 DFFE 1 3 0 3 |74161:74|f74161:sub|QB (|74161:74|f74161:sub|:87)
- 8 - B 12 AND2 0 4 0 1 |74161:74|f74161:sub|:94
- 3 - B 12 DFFE 1 3 0 2 |74161:74|f74161:sub|QC (|74161:74|f74161:sub|:99)
- 1 - B 12 DFFE 1 3 0 1 |74161:74|f74161:sub|QD (|74161:74|f74161:sub|:110)
- 6 - B 03 DFFE 1 2 0 5 |74161:75|f74161:sub|QA (|74161:75|f74161:sub|:9)
- 7 - B 03 AND2 0 2 0 1 |74161:75|f74161:sub|:84
- 4 - B 03 DFFE 1 3 0 4 |74161:75|f74161:sub|QB (|74161:75|f74161:sub|:87)
- 8 - B 03 AND2 0 3 0 1 |74161:75|f74161:sub|:94
- 3 - B 03 DFFE 1 3 0 3 |74161:75|f74161:sub|QC (|74161:75|f74161:sub|:99)
- 5 - B 03 AND2 0 4 0 4 |74161:75|f74161:sub|:104
- 2 - B 03 DFFE 1 3 0 2 |74161:75|f74161:sub|QD (|74161:75|f74161:sub|:110)
- 4 - B 02 DFFE 0 2 1 8 |74273:78|Q8 (|74273:78|:12)
- 2 - B 02 DFFE 0 2 1 8 |74273:78|Q7 (|74273:78|:13)
- 1 - B 02 DFFE 0 2 1 8 |74273:78|Q6 (|74273:78|:14)
- 6 - B 02 DFFE 0 2 1 8 |74273:78|Q5 (|74273:78|:15)
- 5 - B 02 DFFE 0 2 1 8 |74273:78|Q4 (|74273:78|:16)
- 8 - B 02 DFFE 0 2 1 8 |74273:78|Q3 (|74273:78|:17)
- 7 - B 04 DFFE 0 2 1 8 |74273:78|Q2 (|74273:78|:18)
- 7 - B 02 DFFE 0 2 1 8 |74273:78|Q1 (|74273:78|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\documents and settings\user\cpumodel\test_ram.rpt
test_ram
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 25/ 96( 26%) 24/ 48( 50%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 8/16( 50%)
C: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\documents and settings\user\cpumodel\test_ram.rpt
test_ram
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 :62
LCELL 8 :63
Device-Specific Information:c:\documents and settings\user\cpumodel\test_ram.rpt
test_ram
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 161clrn
Device-Specific Information:c:\documents and settings\user\cpumodel\test_ram.rpt
test_ram
** EQUATIONS **
LDAR : INPUT;
memenab : INPUT;
pc_bus : INPUT;
rd : INPUT;
t1 : INPUT;
t2 : INPUT;
we : INPUT;
161clrn : INPUT;
161oad : INPUT;
161pc : INPUT;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC7_B2;
-- Node name is 'adr1'
-- Equation name is 'adr1', type is output
adr1 = _LC7_B4;
-- Node name is 'adr2'
-- Equation name is 'adr2', type is output
adr2 = _LC8_B2;
-- Node name is 'adr3'
-- Equation name is 'adr3', type is output
adr3 = _LC5_B2;
-- Node name is 'adr4'
-- Equation name is 'adr4', type is output
adr4 = _LC6_B2;
-- Node name is 'adr5'
-- Equation name is 'adr5', type is output
adr5 = _LC1_B2;
-- Node name is 'adr6'
-- Equation name is 'adr6', type is output
adr6 = _LC2_B2;
-- Node name is 'adr7'
-- Equation name is 'adr7', type is output
adr7 = _LC4_B2;
-- Node name is 'd0'
-- Equation name is 'd0', type is bidir
d0 = TRI(_LC1_B3, _LC1_B7);
-- Node name is 'd1'
-- Equation name is 'd1', type is bidir
d1 = TRI(_LC1_B5, _LC1_B7);
-- Node name is 'd2'
-- Equation name is 'd2', type is bidir
d2 = TRI(_LC6_B7, _LC1_B7);
-- Node name is 'd3'
-- Equation name is 'd3', type is bidir
d3 = TRI(_LC3_B7, _LC1_B7);
-- Node name is 'd4'
-- Equation name is 'd4', type is bidir
d4 = TRI(_LC8_B7, _LC1_B7);
-- Node name is 'd5'
-- Equation name is 'd5', type is bidir
d5 = TRI(_LC4_B12, _LC1_B7);
-- Node name is 'd6'
-- Equation name is 'd6', type is bidir
d6 = TRI(_LC2_B7, _LC1_B7);
-- Node name is 'd7'
-- Equation name is 'd7', type is bidir
d7 = TRI(_LC5_B5, _LC1_B7);
-- Node name is '|LPM_RAM_IO:81|datatri0~1~3'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ001);
_EQ001 = _EC7_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC7_B & _LC6_B3
# !_LC5_B7 & _LC6_B3;
-- Node name is '|LPM_RAM_IO:81|datatri1~1~3'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ002);
_EQ002 = _EC2_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC2_B & _LC4_B3
# _LC4_B3 & !_LC5_B7;
-- Node name is '|LPM_RAM_IO:81|datatri2~1~3'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = LCELL( _EQ003);
_EQ003 = _EC6_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC6_B & _LC3_B3
# _LC3_B3 & !_LC5_B7;
-- Node name is '|LPM_RAM_IO:81|datatri3~1~3'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ004);
_EQ004 = _EC5_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC5_B & _LC2_B3
# _LC2_B3 & !_LC5_B7;
-- Node name is '|LPM_RAM_IO:81|datatri4~1~3'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ005);
_EQ005 = _EC4_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC4_B & _LC6_B12
# !_LC5_B7 & _LC6_B12;
-- Node name is '|LPM_RAM_IO:81|datatri5~1~3'
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ006);
_EQ006 = _EC8_B & pc_bus
# !_LC5_B7 & pc_bus
# _EC8_B & _LC5_B12
# !_LC5_B7 & _LC5_B12;
-- Node name is '|LPM_RAM_IO:81|datatri6~1~3'
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