📄 jie_pai.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jie_pai.rpt
jie_pai
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jie_pai.rpt
jie_pai
** CLOCK SIGNALS **
Type Fan-out Name
DFF 5 |74175:42|4Q
LCELL 4 :33
INPUT 3 H
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jie_pai.rpt
jie_pai
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 4 :52
INPUT 2 TJ
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jie_pai.rpt
jie_pai
** EQUATIONS **
DP : INPUT;
H : INPUT;
QD : INPUT;
TJ : INPUT;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC2_A23;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC1_A23;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC7_A23;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC3_A23;
-- Node name is 'START'
-- Equation name is 'START', type is output
START = _LC3_A13;
-- Node name is 'T1'
-- Equation name is 'T1', type is output
T1 = _LC5_A13;
-- Node name is 'T2'
-- Equation name is 'T2', type is output
T2 = _LC5_A23;
-- Node name is 'T3'
-- Equation name is 'T3', type is output
T3 = _LC4_A13;
-- Node name is 'T4'
-- Equation name is 'T4', type is output
T4 = _LC8_A13;
-- Node name is '|7474:40|:9' = '|7474:40|1Q'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = DFFE( _LC1_A23, GLOBAL(!H), VCC, VCC, VCC);
-- Node name is '|7474:41|:9' = '|7474:41|1Q'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ001, _LC3_A23, GLOBAL(!TJ), VCC, VCC);
_EQ001 = _LC1_A13 & _LC2_A13;
-- Node name is '|74175:42|:16' = '|74175:42|1Q'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = DFFE( _LC1_A23, _LC8_A23, _LC6_A23, VCC, VCC);
-- Node name is '|74175:42|:15' = '|74175:42|2Q'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = DFFE( _LC7_A23, _LC8_A23, _LC6_A23, VCC, VCC);
-- Node name is '|74175:42|:14' = '|74175:42|3Q'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = DFFE( _LC3_A23, _LC8_A23, _LC6_A23, VCC, VCC);
-- Node name is '|74175:42|:13' = '|74175:42|4Q'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( VCC, _LC8_A23, _LC6_A23, VCC, VCC);
-- Node name is ':15'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ002);
_EQ002 = _LC3_A13 & !_LC3_A23;
-- Node name is ':17'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ003);
_EQ003 = _LC3_A13 & _LC3_A23 & !_LC7_A23;
-- Node name is ':19'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ004);
_EQ004 = !_LC1_A23 & _LC3_A13 & _LC7_A23;
-- Node name is ':20'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ005);
_EQ005 = _LC1_A23 & _LC3_A13;
-- Node name is ':33'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = LCELL( _EQ006);
_EQ006 = _LC4_A23
# H;
-- Node name is ':37'
-- Equation name is '_LC1_A13', type is buried
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( QD);
-- Node name is ':38'
-- Equation name is '_LC2_A13', type is buried
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ007);
_EQ007 = _LC1_A13 & !_LC2_A13
# DP & _LC1_A13 & _LC3_A13;
-- Node name is ':52'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ008);
_EQ008 = !_LC4_A23 & !TJ
# !H & !TJ;
Project Information d:\maxplus2\cpu_design\cpu_module\jie_pai.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,214K
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