cpurom.rpt

简单的CPU设计数字系统实验

  _EQ024 =  _LC5_B18 & !_LC6_B24
         #  _LC1_B21 &  _LC6_B15;

-- Node name is ':467' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = LCELL( _EQ025);
  _EQ025 = !_LC5_B19 &  _LC7_B18 & !_LC8_B18
         #  _LC2_B18 & !_LC8_B18;

-- Node name is ':480' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = LCELL( _EQ026);
  _EQ026 =  _LC1_B21 &  _LC3_B15
         #  a3 & !_LC2_B15;

-- Node name is '~512~1' 
-- Equation name is '~512~1', location is LC5_B22, type is buried.
-- synthesized logic cell 
_LC5_B22 = LCELL( _EQ027);
  _EQ027 = !_LC2_B21 & !_LC6_B22;

-- Node name is ':512' 
-- Equation name is '_LC6_B13', type is buried 
_LC6_B13 = LCELL( _EQ028);
  _EQ028 =  _LC2_B13 &  _LC5_B22 & !_LC7_B15 &  _LC7_B20;

-- Node name is ':519' 
-- Equation name is '_LC8_B13', type is buried 
_LC8_B13 = LCELL( _EQ029);
  _EQ029 =  _LC6_B13 & !_LC6_B24
         #  _LC4_B19 & !_LC6_B24
         #  _LC1_B18;

-- Node name is ':530' 
-- Equation name is '_LC1_B13', type is buried 
_LC1_B13 = LCELL( _EQ030);
  _EQ030 = !_LC5_B19 &  _LC8_B13 & !_LC8_B18
         #  _LC2_B18 & !_LC8_B18;

-- Node name is ':845' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = LCELL( _EQ031);
  _EQ031 = !a3 & !_LC1_B15 & !_LC2_B15;

-- Node name is ':908' 
-- Equation name is '_LC3_B20', type is buried 
_LC3_B20 = LCELL( _EQ032);
  _EQ032 = !a3 & !_LC1_B15 &  _LC2_B15 & !_LC4_B15;

-- Node name is ':971' 
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ033);
  _EQ033 = !a3 & !_LC1_B19 &  _LC6_B20;

-- Node name is '~1034~1' 
-- Equation name is '~1034~1', location is LC6_B20, type is buried.
-- synthesized logic cell 
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = LCELL( _EQ034);
  _EQ034 = !a3 & !_LC4_B15
         #  _LC1_B15
         # !a3 & !_LC2_B15;

-- Node name is ':1034' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ035);
  _EQ035 = !a3 &  _LC1_B19 & !_LC5_B15 &  _LC6_B20;

-- Node name is ':1097' 
-- Equation name is '_LC2_B20', type is buried 
_LC2_B20 = LCELL( _EQ036);
  _EQ036 =  a3 & !_LC4_B15 &  _LC8_B20;

-- Node name is ':1160' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ037);
  _EQ037 =  a3 & !_LC1_B19 &  _LC4_B15 &  _LC8_B20;

-- Node name is '~1223~1' 
-- Equation name is '~1223~1', location is LC3_B18, type is buried.
-- synthesized logic cell 
_LC3_B18 = LCELL( _EQ038);
  _EQ038 = !_LC2_B18 & !_LC8_B18;

-- Node name is ':1223' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = LCELL( _EQ039);
  _EQ039 =  _LC1_B17 &  _LC3_B18 &  _LC7_B15
         #  _LC1_B17 &  _LC3_B18 &  _LC6_B19;

-- Node name is ':1242' 
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = LCELL( _EQ040);
  _EQ040 =  _LC1_B21 &  _LC3_B15
         #  _LC2_B21
         #  _LC6_B22;

-- Node name is ':1266' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = LCELL( _EQ041);
  _EQ041 =  _LC1_B22 & !_LC7_B15 &  _LC7_B20
         #  _LC4_B19;

-- Node name is ':1286' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ042);
  _EQ042 =  _LC3_B18 & !_LC6_B24 &  _LC8_B24
         # !_LC1_B17 &  _LC3_B18;

-- Node name is '~1328~1' 
-- Equation name is '~1328~1', location is LC8_B20, type is buried.
-- synthesized logic cell 
!_LC8_B20 = _LC8_B20~NOT;
_LC8_B20~NOT = LCELL( _EQ043);
  _EQ043 = !_LC6_B20
         # !a3 & !_LC1_B19
         # !a3 & !_LC5_B15;

-- Node name is '~1328~2' 
-- Equation name is '~1328~2', location is LC7_B20, type is buried.
-- synthesized logic cell 
!_LC7_B20 = _LC7_B20~NOT;
_LC7_B20~NOT = LCELL( _EQ044);
  _EQ044 = !_LC8_B20
         #  a3 & !a4 &  _LC2_B19;

-- Node name is ':1329' 
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ045);
  _EQ045 =  _LC1_B22 &  _LC7_B20
         #  _LC7_B15
         #  _LC4_B19;

-- Node name is ':1338' 
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = LCELL( _EQ046);
  _EQ046 = !_LC3_B21 &  _LC3_B24
         #  _LC1_B18
         #  _LC6_B19;

-- Node name is ':1349' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = LCELL( _EQ047);
  _EQ047 =  _LC3_B18 & !_LC5_B19 &  _LC7_B24;

-- Node name is ':1365' 
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = LCELL( _EQ048);
  _EQ048 =  _LC1_B21 &  _LC3_B15
         #  _LC2_B21;

-- Node name is '~1412~1' 
-- Equation name is '~1412~1', location is LC1_B17, type is buried.
-- synthesized logic cell 
_LC1_B17 = LCELL( _EQ049);
  _EQ049 = !_LC1_B18 & !_LC5_B19;

-- Node name is '~1412~2' 
-- Equation name is '~1412~2', location is LC2_B22, type is buried.
-- synthesized logic cell 
_LC2_B22 = LCELL( _EQ050);
  _EQ050 =  _LC1_B17 & !_LC2_B18;

-- Node name is '~1412~3' 
-- Equation name is '~1412~3', location is LC8_B22, type is buried.
-- synthesized logic cell 
_LC8_B22 = LCELL( _EQ051);
  _EQ051 =  _LC4_B22 & !_LC6_B22 & !_LC7_B22 & !_LC8_B18;

-- Node name is ':1412' 
-- Equation name is '_LC3_B22', type is buried 
_LC3_B22 = LCELL( _EQ052);
  _EQ052 =  _LC2_B22 & !_LC6_B24 &  _LC7_B20 &  _LC8_B22;

-- Node name is ':1455' 
-- Equation name is '_LC7_B22', type is buried 
!_LC7_B22 = _LC7_B22~NOT;
_LC7_B22~NOT = LCELL( _EQ053);
  _EQ053 = !_LC4_B19 & !_LC7_B15;

-- Node name is ':1464' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = LCELL( _EQ054);
  _EQ054 = !_LC6_B24 &  _LC7_B15
         #  _LC4_B19 & !_LC6_B24
         #  _LC1_B18;

-- Node name is ':1475' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ055);
  _EQ055 =  _LC1_B24 & !_LC5_B19 & !_LC8_B18
         #  _LC2_B18 & !_LC8_B18;

-- Node name is '~1488~1' 
-- Equation name is '~1488~1', location is LC3_B13, type is buried.
-- synthesized logic cell 
_LC3_B13 = LCELL( _EQ056);
  _EQ056 =  a3 & !_LC4_B15
         #  a3 & !_LC1_B19;

-- Node name is ':1512' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ057);
  _EQ057 = !_LC7_B20
         #  _LC2_B13 &  _LC5_B22
         #  _LC3_B13 &  _LC5_B22;

-- Node name is '~1524~1' 
-- Equation name is '~1524~1', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ058);
  _EQ058 =  _LC3_B21
         #  _LC6_B19;

-- Node name is ':1524' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = LCELL( _EQ059);
  _EQ059 =  _LC4_B13 & !_LC7_B15
         #  _LC6_B24
         #  _LC4_B19;

-- Node name is ':1536' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ060);
  _EQ060 =  _LC8_B18
         #  _LC1_B17 & !_LC2_B18 &  _LC5_B13;



Project Information               d:\maxplus2\cpu_design\cpu_module\cpurom.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,641K