cpurom.rpt

简单的CPU设计数字系统实验

   -      5     -    B    13        OR2                0    4    0    1  :1524
   -      7     -    B    13        OR2                0    4    1    0  :1536


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:      d:\maxplus2\cpu_design\cpu_module\cpurom.rpt
cpurom

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:      11/ 96( 11%)     0/ 48(  0%)    20/ 48( 41%)    0/16(  0%)      9/16( 56%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     2/ 48(  4%)    0/16(  0%)      2/16( 12%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
22:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
23:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
24:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:      d:\maxplus2\cpu_design\cpu_module\cpurom.rpt
cpurom

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
a4       : INPUT;

-- Node name is 'ar0' 
-- Equation name is 'ar0', type is output 
ar0      =  _LC7_B13;

-- Node name is 'ar1' 
-- Equation name is 'ar1', type is output 
ar1      =  _LC4_B18;

-- Node name is 'ar2' 
-- Equation name is 'ar2', type is output 
ar2      =  _LC3_B22;

-- Node name is 'ar3' 
-- Equation name is 'ar3', type is output 
ar3      =  _LC5_B24;

-- Node name is 'ar4' 
-- Equation name is 'ar4', type is output 
ar4      =  _LC2_B24;

-- Node name is 'en_io' 
-- Equation name is 'en_io', type is output 
en_io    =  _LC4_B20;

-- Node name is 'l_and' 
-- Equation name is 'l_and', type is output 
l_and    =  _LC3_B20;

-- Node name is 'l_or' 
-- Equation name is 'l_or', type is output 
l_or     =  _LC5_B20;

-- Node name is 'move' 
-- Equation name is 'move', type is output 
move     =  _LC6_B22;

-- Node name is 'm_pc' 
-- Equation name is 'm_pc', type is output 
m_pc     =  _LC2_B20;

-- Node name is 'm_ri' 
-- Equation name is 'm_ri', type is output 
m_ri     =  _LC3_B21;

-- Node name is 'mul' 
-- Equation name is 'mul', type is output 
mul      =  _LC1_B20;

-- Node name is 'pc_ar' 
-- Equation name is 'pc_ar', type is output 
pc_ar    =  _LC6_B18;

-- Node name is 'pc_in' 
-- Equation name is 'pc_in', type is output 
pc_in    =  _LC1_B13;

-- Node name is 'plus' 
-- Equation name is 'plus', type is output 
plus     =  _LC1_B15;

-- Node name is 'p1' 
-- Equation name is 'p1', type is output 
p1       =  _LC5_B19;

-- Node name is 'ram_ar' 
-- Equation name is 'ram_ar', type is output 
ram_ar   =  _LC4_B24;

-- Node name is 'ram_ir_dr' 
-- Equation name is 'ram_ir_dr', type is output 
ram_ir_dr =  _LC7_B19;

-- Node name is 'ri_m' 
-- Equation name is 'ri_m', type is output 
ri_m     =  _LC3_B19;

-- Node name is 'sub' 
-- Equation name is 'sub', type is output 
sub      =  _LC8_B15;

-- Node name is 'sw_pc' 
-- Equation name is 'sw_pc', type is output 
sw_pc    =  _LC8_B18;

-- Node name is ':96' 
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ001);
  _EQ001 = !a0 & !a4 &  _LC6_B15;

-- Node name is ':102' 
-- Equation name is '_LC2_B18', type is buried 
!_LC2_B18 = _LC2_B18~NOT;
_LC2_B18~NOT = LCELL( _EQ002);
  _EQ002 = !_LC6_B15
         #  a4
         # !a0;

-- Node name is '~108~1' 
-- Equation name is '~108~1', location is LC7_B19, type is buried.
-- synthesized logic cell 
!_LC7_B19 = _LC7_B19~NOT;
_LC7_B19~NOT = LCELL( _EQ003);
  _EQ003 =  a4
         # !_LC8_B19;

-- Node name is ':108' 
-- Equation name is '_LC5_B19', type is buried 
!_LC5_B19 = _LC5_B19~NOT;
_LC5_B19~NOT = LCELL( _EQ004);
  _EQ004 =  a4
         # !_LC8_B19;

-- Node name is '~114~1' 
-- Equation name is '~114~1', location is LC6_B15, type is buried.
-- synthesized logic cell 
_LC6_B15 = LCELL( _EQ005);
  _EQ005 = !a1 & !a2 & !a3;

-- Node name is ':114' 
-- Equation name is '_LC1_B18', type is buried 
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ006);
  _EQ006 = !_LC6_B15
         # !_LC1_B21;

-- Node name is ':120' 
-- Equation name is '_LC6_B19', type is buried 
_LC6_B19 = LCELL( _EQ007);
  _EQ007 =  a3 &  a4 &  _LC2_B19;

-- Node name is ':126' 
-- Equation name is '_LC3_B21', type is buried 
!_LC3_B21 = _LC3_B21~NOT;
_LC3_B21~NOT = LCELL( _EQ008);
  _EQ008 = !_LC3_B15
         #  a4
         # !a0;

-- Node name is '~132~1' 
-- Equation name is '~132~1', location is LC2_B19, type is buried.
-- synthesized logic cell 
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ009);
  _EQ009 =  a0
         #  a2
         # !a1;

-- Node name is '~132~2' 
-- Equation name is '~132~2', location is LC8_B19, type is buried.
-- synthesized logic cell 
!_LC8_B19 = _LC8_B19~NOT;
_LC8_B19~NOT = LCELL( _EQ010);
  _EQ010 =  a3
         # !_LC2_B19;

-- Node name is ':132' 
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ011);
  _EQ011 =  a4 &  _LC8_B19;

-- Node name is ':138' 
-- Equation name is '_LC7_B15', type is buried 
!_LC7_B15 = _LC7_B15~NOT;
_LC7_B15~NOT = LCELL( _EQ012);
  _EQ012 =  a2
         # !a1
         # !_LC1_B21
         # !a3;

-- Node name is ':144' 
-- Equation name is '_LC3_B19', type is buried 
!_LC3_B19 = _LC3_B19~NOT;
_LC3_B19~NOT = LCELL( _EQ013);
  _EQ013 = !a3
         # !_LC2_B19
         #  a4;

-- Node name is ':150' 
-- Equation name is '_LC1_B15', type is buried 
!_LC1_B15 = _LC1_B15~NOT;
_LC1_B15~NOT = LCELL( _EQ014);
  _EQ014 =  a2
         # !a1
         # !_LC1_B21
         #  a3;

-- Node name is '~156~1' 
-- Equation name is '~156~1', location is LC2_B15, type is buried.
-- synthesized logic cell 
!_LC2_B15 = _LC2_B15~NOT;
_LC2_B15~NOT = LCELL( _EQ015);
  _EQ015 = !a0 & !a1 &  a2 &  a4;

-- Node name is '~162~1' 
-- Equation name is '~162~1', location is LC4_B15, type is buried.
-- synthesized logic cell 
!_LC4_B15 = _LC4_B15~NOT;
_LC4_B15~NOT = LCELL( _EQ016);
  _EQ016 = !a1 &  a2 &  _LC1_B21;

-- Node name is '~168~1' 
-- Equation name is '~168~1', location is LC1_B19, type is buried.
-- synthesized logic cell 
!_LC1_B19 = _LC1_B19~NOT;
_LC1_B19~NOT = LCELL( _EQ017);
  _EQ017 = !a0 &  a1 &  a2 &  a4;

-- Node name is '~174~1' 
-- Equation name is '~174~1', location is LC5_B15, type is buried.
-- synthesized logic cell 
!_LC5_B15 = _LC5_B15~NOT;
_LC5_B15~NOT = LCELL( _EQ018);
  _EQ018 =  a1 &  a2 &  _LC1_B21;

-- Node name is ':180' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = LCELL( _EQ019);
  _EQ019 =  a3 & !_LC5_B15;

-- Node name is ':186' 
-- Equation name is '_LC2_B21', type is buried 
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ020);
  _EQ020 = !a4
         #  a0
         # !_LC3_B15;

-- Node name is '~192~1' 
-- Equation name is '~192~1', location is LC3_B15, type is buried.
-- synthesized logic cell 
!_LC3_B15 = _LC3_B15~NOT;
_LC3_B15~NOT = LCELL( _EQ021);
  _EQ021 =  a2
         #  a1
         # !a3;

-- Node name is '~198~1' 
-- Equation name is '~198~1', location is LC1_B21, type is buried.
-- synthesized logic cell 
_LC1_B21 = LCELL( _EQ022);
  _EQ022 =  a0 &  a4;

-- Node name is ':447' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ023);
  _EQ023 =  _LC1_B21 &  _LC3_B15
         #  a4 &  _LC8_B19;

-- Node name is ':456' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ024);