alur.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 922 行 · 第 1/5 页
RPT
922 行
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alur.rpt
alur
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
A14 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
A15 6/ 8( 75%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A17 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
A19 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
A20 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
A21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
A22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A23 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
A24 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B3 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
B4 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B5 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 9/22( 40%)
B6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B9 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
B10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
B11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
B12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
B13 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B14 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
B15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
B16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
B17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
B18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
B20 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 12/22( 54%)
B21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
B22 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
B23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
B24 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 22/53 ( 41%)
Total logic cells used: 225/576 ( 39%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.55/4 ( 88%)
Total fan-in: 800/2304 ( 34%)
Total input pins required: 19
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 225
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 52/ 576 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 2 6 0 8 8 8 7 8 8 7 2 72/0
B: 8 1 2 8 8 1 1 0 8 8 8 8 0 6 8 8 8 8 8 8 8 8 6 8 8 153/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 1 2 8 8 1 1 0 8 8 8 8 0 14 10 14 8 16 16 16 15 16 14 15 10 225/0
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alur.rpt
alur
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- INPUT 0 0 0 19 a0
52 - - - 19 INPUT 0 0 0 19 a1
84 - - - -- INPUT 0 0 0 23 a2
44 - - - -- INPUT 0 0 0 23 a3
43 - - - -- INPUT 0 0 0 23 a4
49 - - - 16 INPUT 0 0 0 24 a5
1 - - - -- INPUT 0 0 0 22 a6
78 - - - 24 INPUT 0 0 0 19 a7
65 - - B -- INPUT 0 0 0 23 b0
23 - - B -- INPUT 0 0 0 24 b1
21 - - B -- INPUT 0 0 0 21 b2
42 - - - -- INPUT 0 0 0 26 b3
51 - - - 18 INPUT 0 0 0 24 b4
2 - - - -- INPUT 0 0 0 21 b5
50 - - - 17 INPUT 0 0 0 22 b6
79 - - - 24 INPUT 0 0 0 18 b7
47 - - - 14 INPUT 0 0 0 23 s0
48 - - - 15 INPUT 0 0 0 9 s1
53 - - - 20 INPUT 0 0 0 9 s2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alur.rpt
alur
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - A -- OUTPUT 0 1 0 0 cout
25 - - B -- OUTPUT 0 1 0 0 r0
24 - - B -- OUTPUT 0 1 0 0 r1
67 - - B -- OUTPUT 0 1 0 0 r2
66 - - B -- OUTPUT 0 1 0 0 r3
64 - - B -- OUTPUT 0 1 0 0 r4
71 - - A -- OUTPUT 0 1 0 0 r5
72 - - A -- OUTPUT 0 1 0 0 r6
73 - - A -- OUTPUT 0 1 0 0 r7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alur.rpt
alur
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 23 OR2 4 0 0 2 |alu:2|LPM_ADD_SUB:5|addcore:adder|pcarry1
- 1 - B 23 OR2 2 1 0 2 |alu:2|LPM_ADD_SUB:5|addcore:adder|pcarry2
- 8 - B 21 OR2 2 1 0 2 |alu:2|LPM_ADD_SUB:5|addcore:adder|pcarry3
- 4 - B 21 OR2 2 1 0 2 |alu:2|LPM_ADD_SUB:5|addcore:adder|pcarry4
- 1 - A 21 OR2 2 1 0 2 |alu:2|LPM_ADD_SUB:5|addcore:adder|pcarry5
- 7 - B 09 OR2 4 0 0 1 |alu:2|LPM_ADD_SUB:5|addcore:adder|:156
- 7 - B 23 OR2 2 1 0 1 |alu:2|LPM_ADD_SUB:5|addcore:adder|:157
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