📄 xx.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 24 AND2 s 0 3 0 3 ~38~1
- 7 - C 24 AND2 s 0 3 0 3 ~52~1
- 6 - C 24 DFFE + 0 4 1 3 |7474:33|1Q (|7474:33|:9)
- 1 - C 24 DFFE + 0 3 1 3 |7474:33|2Q (|7474:33|:10)
- 3 - C 24 DFFE + 0 3 1 3 |7474:34|1Q (|7474:34|:9)
- 8 - C 24 DFFE + 0 4 1 4 |7474:34|2Q (|7474:34|:10)
- 2 - C 24 DFFE + 0 3 1 3 |7474:35|1Q (|7474:35|:9)
- 4 - C 24 DFFE + 0 2 1 3 |7474:35|2Q (|7474:35|:10)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\07\xx.rpt
xx
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\07\xx.rpt
xx
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 CLK
Device-Specific Information: d:\maxplus2\07\xx.rpt
xx
** EQUATIONS **
CLK : INPUT;
-- Node name is 'GW0'
-- Equation name is 'GW0', type is output
GW0 = _LC1_C24;
-- Node name is 'GW1'
-- Equation name is 'GW1', type is output
GW1 = _LC4_C24;
-- Node name is 'GW2'
-- Equation name is 'GW2', type is output
GW2 = _LC8_C24;
-- Node name is 'SW0'
-- Equation name is 'SW0', type is output
SW0 = _LC6_C24;
-- Node name is 'SW1'
-- Equation name is 'SW1', type is output
SW1 = _LC2_C24;
-- Node name is 'SW2'
-- Equation name is 'SW2', type is output
SW2 = _LC3_C24;
-- Node name is '|7474:33|:9' = '|7474:33|1Q'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = _LC1_C24 & !_LC3_C24 & _LC5_C24 & !_LC8_C24;
-- Node name is '|7474:33|:10' = '|7474:33|2Q'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !_LC1_C24 & _LC3_C24 & _LC5_C24 & !_LC8_C24;
-- Node name is '|7474:34|:9' = '|7474:34|1Q'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !_LC1_C24 & !_LC3_C24 & _LC5_C24 & _LC8_C24;
-- Node name is '|7474:34|:10' = '|7474:34|2Q'
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC2_C24 & !_LC4_C24 & !_LC6_C24 & _LC7_C24;
-- Node name is '|7474:35|:9' = '|7474:35|1Q'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !_LC2_C24 & _LC4_C24 & !_LC6_C24 & _LC7_C24;
-- Node name is '|7474:35|:10' = '|7474:35|2Q'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = !_LC2_C24 & !_LC4_C24 & _LC7_C24;
-- Node name is '~38~1'
-- Equation name is '~38~1', location is LC5_C24, type is buried.
-- synthesized logic cell
_LC5_C24 = LCELL( _EQ007);
_EQ007 = !_LC2_C24 & !_LC4_C24 & !_LC6_C24;
-- Node name is '~52~1'
-- Equation name is '~52~1', location is LC7_C24, type is buried.
-- synthesized logic cell
_LC7_C24 = LCELL( _EQ008);
_EQ008 = !_LC1_C24 & !_LC3_C24 & !_LC8_C24;
Project Information d:\maxplus2\07\xx.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,815K
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