cpumodel.hif
来自「简单的CPU设计数字系统实验」· HIF 代码 · 共 539 行 · 第 1/3 页
HIF
539 行
29 [END_ADDER=1,width=8,size=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result15,result14,result13,result12,result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,data7_15,data7_14,data7_13,data7_12,data7_11,data7_10,data7_9,data7_8,data7_7,data7_6,data7_5,data7_4,data7_3,data7_2,data7_1,data7_0,data6_15,data6_14,data6_13,data6_12,data6_11,data6_10,data6_9,data6_8,data6_7,data6_6,data6_5,data6_4,data6_3,data6_2,data6_1,data6_0,data5_15,data5_14,data5_13,data5_12,data5_11,data5_10,data5_9,data5_8,data5_7,data5_6,data5_5,data5_4,data5_3,data5_2,data5_1,data5_0,data4_15,data4_14,data4_13,data4_12,data4_11,data4_10,data4_9,data4_8,data4_7,data4_6,data4_5,data4_4,data4_3,data4_2,data4_1,data4_0,data3_15,data3_14,data3_13,data3_12,data3_11,data3_10,data3_9,data3_8,data3_7,data3_6,data3_5,data3_4,data3_3,data3_2,data3_1,data3_0,data2_15,data2_14,data2_13,data2_12,data2_11,data2_10,data2_9,data2_8,data2_7,data2_6,data2_5,data2_4,data2_3,data2_2,data2_1,data2_0,data1_15,data1_14,data1_13,data1_12,data1_11,data1_10,data1_9,data1_8,data1_7,data1_6,data1_5,data1_4,data1_3,data1_2,data1_1,data1_0,data0_15,data0_14,data0_13,data0_12,data0_11,data0_10,data0_9,data0_8,data0_7,data0_6,data0_5,data0_4,data0_3,data0_2,data0_1,data0_0];
47 [END_ADDER=1,width=9,size=16,USE_LPM_FOR_AHDL_OPERATORS=OFF] [data0_0,data0_1,data0_2,data0_3,data0_4,data0_5,data0_6,data0_7,data0_8,data0_9,data0_10,data0_11,data0_12,data0_13,data0_14,data0_15,data1_0,data1_1,data1_2,data1_3,data1_4,data1_5,data1_6,data1_7,data1_8,data1_9,data1_10,data1_11,data1_12,data1_13,data1_14,data1_15,data2_0,data2_1,data2_2,data2_3,data2_4,data2_5,data2_6,data2_7,data2_8,data2_9,data2_10,data2_11,data2_12,data2_13,data2_14,data2_15,data3_0,data3_1,data3_2,data3_3,data3_4,data3_5,data3_6,data3_7,data3_8,data3_9,data3_10,data3_11,data3_12,data3_13,data3_14,data3_15,data4_0,data4_1,data4_2,data4_3,data4_4,data4_5,data4_6,data4_7,data4_8,data4_9,data4_10,data4_11,data4_12,data4_13,data4_14,data4_15,data5_0,data5_1,data5_2,data5_3,data5_4,data5_5,data5_6,data5_7,data5_8,data5_9,data5_10,data5_11,data5_12,data5_13,data5_14,data5_15,data6_0,data6_1,data6_2,data6_3,data6_4,data6_5,data6_6,data6_7,data6_8,data6_9,data6_10,data6_11,data6_12,data6_13,data6_14,data6_15,data7_0,data7_1,data7_2,data7_3,data7_4,data7_5,data7_6,data7_7,data7_8,data7_9,data7_10,data7_11,data7_12,data7_13,data7_14,data7_15,data8_0,data8_1,data8_2,data8_3,data8_4,data8_5,data8_6,data8_7,data8_8,data8_9,data8_10,data8_11,data8_12,data8_13,data8_14,data8_15,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10,result11,result12,result13,result14,result15];
}
}
multcore.tdf
{
multcore [CARRY_CHAIN,DEVICE_FAMILY,OP_MODE=0,MAXIMIZE_SPEED=5,USE_EAB=OFF,ONE_INPUT_IS_CONSTANT=NO,LATENCY=0,LPM_REPRESENTATION=UNSIGNED,widthb,widtha,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc,lpm_add_sub.inc,csa_add.inc,mpar_add.inc,muleabz.inc,mul_lfrg.inc,mul_boothc.inc]
{
28 [CARRY_CHAIN=IGNORE,DEVICE_FAMILY=FLEX10K,OP_MODE=0,MAXIMIZE_SPEED=5,USE_EAB=OFF,ONE_INPUT_IS_CONSTANT=NO,LATENCY=1,LPM_REPRESENTATION=UNSIGNED,widthb=8,widtha=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result15,result14,result13,result12,result11,result10,result9,result8,dataa7,dataa6,dataa5,dataa4,dataa3,dataa2,dataa1,dataa0,datab7,datab6,datab5,datab4,datab3,datab2,datab1,datab0];
46 [CARRY_CHAIN=IGNORE,DEVICE_FAMILY=FLEX10K,OP_MODE=0,MAXIMIZE_SPEED=5,USE_EAB=OFF,ONE_INPUT_IS_CONSTANT=NO,LATENCY=1,LPM_REPRESENTATION=SIGNED,widthb=8,widtha=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,result8,result9,result10,result11,result12,result13,result14,result15];
}
}
lpm_mult.tdf
{
lpm_mult [CARRY_CHAIN,DEVICE_FAMILY,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=1,USE_EAB=OFF,INPUT_B_IS_CONSTANT=NO,INPUT_A_IS_CONSTANT=NO,LATENCY=0,LPM_PIPELINE=0,LPM_REPRESENTATION=UNSIGNED,LPM_WIDTHS,LPM_WIDTHR=0,LPM_WIDTHP,LPM_WIDTHB,LPM_WIDTHA,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc,lpm_add_sub.inc,multcore.inc,bypassff.inc,altshift.inc]
{
27 [CARRY_CHAIN=IGNORE,DEVICE_FAMILY=FLEX10K,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=1,USE_EAB=OFF,INPUT_B_IS_CONSTANT=NO,INPUT_A_IS_CONSTANT=NO,LATENCY=0,LPM_PIPELINE=0,LPM_REPRESENTATION=UNSIGNED,LPM_WIDTHS=8,LPM_WIDTHR=0,LPM_WIDTHP=8,LPM_WIDTHB=8,LPM_WIDTHA=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,result1,result2,result3,result4,result5,result6,result7,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7];
45 [CARRY_CHAIN=IGNORE,DEVICE_FAMILY=FLEX10K,OPTIMIZE_FOR_SPEED=5,MAXIMIZE_SPEED=1,USE_EAB=OFF,INPUT_B_IS_CONSTANT=NO,INPUT_A_IS_CONSTANT=NO,LATENCY=0,LPM_PIPELINE=0,LPM_REPRESENTATION=SIGNED,LPM_WIDTHS=8,LPM_WIDTHR=0,LPM_WIDTHP=8,LPM_WIDTHB=8,LPM_WIDTHA=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dataa7,dataa6,dataa5,dataa4,dataa3,dataa2,dataa1,dataa0,datab7,datab6,datab5,datab4,datab3,datab2,datab1,datab0,result7,result6,result5,result4,result3,result2,result1,result0];
}
}
lpm_and.tdf
{
lpm_and [DEVICE_FAMILY,CASCADE_CHAIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH=32,LPM_SIZE,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
{
23 [DEVICE_FAMILY=FLEX10K,CASCADE_CHAIN=IGNORE,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,LPM_SIZE=2,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,result1,result2,result3,result4,result5,result6,result7,data0_0,data0_1,data0_2,data0_3,data0_4,data0_5,data0_6,data0_7,data1_0,data1_1,data1_2,data1_3,data1_4,data1_5,data1_6,data1_7];
}
}
lpm_or.tdf
{
lpm_or [DEVICE_FAMILY,CASCADE_CHAIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH=32,LPM_SIZE,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
{
22 [DEVICE_FAMILY=FLEX10K,CASCADE_CHAIN=IGNORE,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,LPM_SIZE=2,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,result1,result2,result3,result4,result5,result6,result7,data0_0,data0_1,data0_2,data0_3,data0_4,data0_5,data0_6,data0_7,data1_0,data1_1,data1_2,data1_3,data1_4,data1_5,data1_6,data1_7];
}
}
muxlut.tdf
{
muxlut [CASCADE_CHAIN,LOCAL=0,REM_LATENCY,LATENCY,TOT_LEVELS,LEVEL,SIZE,USE_LPM_FOR_AHDL_OPERATORS] [muxlut.inc,altshift.inc]
{
26 [CASCADE_CHAIN=IGNORE,LOCAL=0,LATENCY=0,TOT_LEVELS=1,LEVEL=0,SIZE=4,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result,data3,data2,data1,data0,select1,select0];
20 [CASCADE_CHAIN=IGNORE,LOCAL=0,LATENCY=0,TOT_LEVELS=1,LEVEL=0,SIZE=4,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result,data3,data2,data1,data0,select1,select0,clock,aclr];
35 [CASCADE_CHAIN=IGNORE,LOCAL=0,LATENCY=0,TOT_LEVELS=1,LEVEL=0,SIZE=2,USE_LPM_FOR_AHDL_OPERATORS=OFF] [select0,data0,data1,result];
}
}
lpm_mux.tdf
{
lpm_mux [LPM_PIPELINE=0,LPM_WIDTHS,LPM_SIZE,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [muxlut.inc,bypassff.inc,altshift.inc]
{
24 [LPM_PIPELINE=0,LPM_WIDTHS=2,LPM_SIZE=4,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,result1,result2,result3,result4,result5,result6,result7,sel0,sel1,data0_0,data0_1,data0_2,data0_3,data0_4,data0_5,data0_6,data0_7,data1_0,data1_1,data1_2,data1_3,data1_4,data1_5,data1_6,data1_7,data2_0,data2_1,data2_2,data2_3,data2_4,data2_5,data2_6,data2_7,data3_0,data3_1,data3_2,data3_3,data3_4,data3_5,data3_6,data3_7];
18 [LPM_PIPELINE=1,LPM_WIDTHS=2,LPM_SIZE=4,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,result1,result2,result3,result4,result5,result6,result7,sel0,sel1,clock,data0_0,data0_1,data0_2,data0_3,data0_4,data0_5,data0_6,data0_7,data1_0,data1_1,data1_2,data1_3,data1_4,data1_5,data1_6,data1_7,data2_0,data2_1,data2_2,data2_3,data2_4,data2_5,data2_6,data2_7,data3_0,data3_1,data3_2,data3_3,data3_4,data3_5,data3_6,data3_7];
44 [LPM_PIPELINE=0,LPM_WIDTHS=1,LPM_SIZE=2,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [data1_7,data1_6,data1_5,data1_4,data1_3,data1_2,data1_1,data1_0,data0_7,data0_6,data0_5,data0_4,data0_3,data0_2,data0_1,data0_0,sel0,result7,result6,result5,result4,result3,result2,result1,result0];
33 [LPM_PIPELINE=0,LPM_WIDTHS=1,LPM_SIZE=2,LPM_WIDTH=1,USE_LPM_FOR_AHDL_OPERATORS=OFF] [sel0,data0_0,data1_0,result0];
}
}
74244.gdf
{
74244 [] []
{
16 [] [];
}
}
altram.tdf
{
altram [DEVICE_FAMILY,USE_EAB=ON,REGISTERINPUTMODE=DEFAULT,FILE=NO_FILE,NUMWORDS,AD_WIDTH,WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [memmodes.inc,lpm_decode.inc,lpm_mux.inc,aglobal.inc]
{
82 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="c:\documents and settings\user\md\uprog00.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
74 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="c:\documents and settings\user\cpumodel\uprog00.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
72 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\uprog00.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
70 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\upr.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
68 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\uprog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
15 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="d:\maxplus2\cpu_design\cpu_module\prog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
43 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="d:\maxplus2\cpu_model0\uprog.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
}
}
lpm_ram_io.tdf
{
lpm_ram_io [DEVICE_FAMILY,LPM_FILE=NO_FILE,LPM_OUTDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS,LPM_WIDTHAD,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [altram.inc,lpm_mux.inc,lpm_decode.inc,aglobal.inc]
{
81 [DEVICE_FAMILY=FLEX10K,LPM_FILE="c:\documents and settings\user\md\uprog00.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
73 [DEVICE_FAMILY=FLEX10K,LPM_FILE="c:\documents and settings\user\cpumodel\uprog00.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
71 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\uprog00.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
69 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\upr.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
67 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\uprog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
14 [DEVICE_FAMILY=FLEX10K,LPM_FILE="d:\maxplus2\cpu_design\cpu_module\prog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
42 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\maxplus2\cpu_model0\uprog.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
}
}
f74161.gdf
{
f74161 [] []
{
12 [] [];
}
}
74161.tdf
{
74161 [DEVICE_FAMILY,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
{
13 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [ENP,CLK,CLRN,RCO,B,C,D,ENT,QA,QB,QC,QD,A,LDN];
11 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [ENP,CLK,CLRN,B,C,D,ENT,QA,QB,QC,QD,A,LDN];
}
}
declut.tdf
{
declut [LATENCY,TOT_LEVELS,STAGE,width,USE_LPM_FOR_AHDL_OPERATORS] [declut.inc,bypassff.inc]
{
5 [LATENCY=0,TOT_LEVELS=1,STAGE=0,width=2,USE_LPM_FOR_AHDL_OPERATORS=OFF] [eq3,eq2,eq1,eq0,data1,data0,enable];
}
}
altshift.tdf
{
altshift [DEPTH=0,WIDTH=4,USE_LPM_FOR_AHDL_OPERATORS] []
{
34 [DEPTH=0,WIDTH=1,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result0,data0];
55 [DEPTH=0,WIDTH=20,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result19,result18,result17,result16,result15,result14,result13,result12,result11,result10,result9,result8,result7,result6,result5,result4,result3,result2,result1,result0,data19,data18,data17,data16,data15,data14,data13,data12,data11,data10,data9,data8,data7,data6,data5,data4,data3,data2,data1,data0];
25 [DEPTH=0,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result7,result6,result5,result4,result3,result2,result1,result0,data7,data6,data5,data4,data3,data2,data1,data0];
19 [DEPTH=1,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result7,result6,result5,result4,result3,result2,result1,result0,data7,data6,data5,data4,data3,data2,data1,data0,clock,aclr];
4 [DEPTH=0,WIDTH=4,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result3,result2,result1,result0,data3,data2,data1,data0];
}
}
lpm_decode.tdf
{
lpm_decode [DEVICE_FAMILY,CASCADE_CHAIN=MANUAL,LPM_PIPELINE=0,LPM_DECODES,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [declut.inc,altshift.inc,lpm_compare.inc,lpm_constant.inc,aglobal.inc]
{
3 [DEVICE_FAMILY=FLEX10K,CASCADE_CHAIN=IGNORE,LPM_PIPELINE=0,LPM_DECODES=4,LPM_WIDTH=2,USE_LPM_FOR_AHDL_OPERATORS=OFF] [data0,data1,enable,eq0,eq1,eq2,eq3];
}
}
7474.gdf
{
7474 [] []
{
37 [] [];
}
}
74273.gdf
{
74273 [] []
{
10 [] [];
}
}
mux.tdf
{
mux [WIDTHS,WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_mux.inc]
{
32 [WIDTHS=1,WIDTH=2,USE_LPM_FOR_AHDL_OPERATORS=OFF] [result,data1,data0,sel0];
}
}
and5.gdf
{
and5 [] []
{
65 [] [];
}
}
7404.gdf
{
7404 [] []
{
64 [] [];
}
}
cpumodel.gdf
{
cpumodel [] []
{
0 [] [];
}
}
}
TREE
{
cpumodel::(0,0):(0): cpumodel.gdf
{
lpm_decode::(0,0):(63): lpm_decode.tdf
{
altshift:4:(76,2):(37,external_latency_ffs): altshift.tdf;
declut:5:(95,5):(51,decoder): declut.tdf;
}
shutong::(0,0):(68): shutong.gdf
{
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