📄 alureg.pin
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-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "alureg" ASSIGNED TO AN EPF10K10LC84-3
CLKJP : 1
tj : 2
ALU_BUS : 3
VCCINT : 4
sb1 : 5
sa1 : 6
D7 : 7
RESERVED : 8
s2 : 9
RESERVED : 10
in0 : 11
DATA0 : 12
DCLK : 13
nCE : 14
TDI : 15
CN4 : 16
D3 : 17
D5 : 18
D4 : 19
VCCINT : 20
SW_BUS : 21
in2 : 22
r_bus : 23
RESERVED : 24
RESERVED : 25
GNDINT : 26
D6 : 27
D0 : 28
R0_6 : 29
t1 : 30
MSEL0 : 31
MSEL1 : 32
VCCINT : 33
nCONFIG : 34
in4 : 35
R0_4 : 36
in6 : 37
in5 : 38
RESERVED : 39
VCCINT : 40
GNDINT : 41
sa0 : 42
s0 : 43
sb0 : 44
VCCINT : 45
GNDINT : 46
RESERVED : 47
RESERVED : 48
RESERVED : 49
R0_3 : 50
DP : 51
LDR1 : 52
LDR3 : 53
RESERVED : 54
nSTATUS : 55
TRST : 56
TMS : 57
R0_1 : 58
R0_7 : 59
R0_2 : 60
R0_0 : 61
R0_5 : 62
VCCINT : 63
D1 : 64
in1 : 65
t3 : 66
D2 : 67
GNDINT : 68
RESERVED : 69
t2 : 70
in3 : 71
LDDR1 : 72
in7 : 73
TDO : 74
nCEO : 75
CONF_DONE : 76
TCK : 77
t4 : 78
LDR2 : 79
QD : 80
LDR0 : 81
GNDINT : 82
LDDR2 : 83
s1 : 84
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