📄 cpumodel.rpt
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Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 5 0 0 0 0 13/0
B: 8 8 2 8 8 0 8 0 8 7 8 8 0 7 0 8 0 8 0 8 8 5 7 8 8 140/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 7 8 2 8 3 8 8 8 7 8 8 8 0 8 8 8 8 8 8 8 7 8 8 7 8 177/0
E: 0 8 0 0 0 0 0 8 8 0 8 0 0 2 8 8 7 8 8 7 8 2 2 7 6 105/0
F: 0 0 0 0 0 0 7 0 0 0 1 0 8 0 8 8 8 0 0 1 0 0 8 3 8 52/8
Total: 15 24 4 16 11 8 23 16 23 15 25 16 8 17 24 32 23 24 16 32 28 15 25 25 30 487/8
Device-Specific Information: f:\md\cpumodel.rpt
cpumodel
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 13 INPUT 0 0 0 3 CLKJP
87 - - E -- INPUT 0 0 0 27 clr
86 - - E -- INPUT 0 0 0 1 DP
31 - - F -- BIDIR 0 1 0 9 d0
32 - - F -- BIDIR 0 1 0 9 d1
33 - - F -- BIDIR 0 1 0 9 d2
36 - - - 24 BIDIR 0 1 0 9 d3
37 - - - 23 BIDIR 0 1 0 9 d4
38 - - - 22 BIDIR 0 1 0 9 d5
39 - - - 21 BIDIR 0 1 0 9 d6
41 - - - 20 BIDIR 0 1 0 10 d7
83 - - E -- INPUT 0 0 0 1 in0
82 - - E -- INPUT 0 0 0 1 in1
81 - - F -- INPUT 0 0 0 1 in2
80 - - F -- INPUT 0 0 0 1 in3
79 - - F -- INPUT 0 0 0 1 in4
78 - - F -- INPUT 0 0 0 1 in5
73 - - - 01 INPUT 0 0 0 1 in6
72 - - - 03 INPUT 0 0 0 1 in7
88 - - D -- INPUT 0 0 0 1 qd
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\md\cpumodel.rpt
cpumodel
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - D -- OUTPUT 0 1 0 0 ar0
22 - - D -- OUTPUT 0 1 0 0 ar1
23 - - D -- OUTPUT 0 1 0 0 ar2
26 - - E -- OUTPUT 0 1 0 0 ar3
27 - - E -- OUTPUT 0 1 0 0 ar4
28 - - E -- OUTPUT 0 1 0 0 ar5
29 - - E -- OUTPUT 0 1 0 0 ar6
30 - - F -- OUTPUT 0 1 0 0 ar7
9 - - B -- OUTPUT 0 1 0 0 a0
10 - - B -- OUTPUT 0 1 0 0 a1
12 - - C -- OUTPUT 0 1 0 0 a2
13 - - C -- OUTPUT 0 1 0 0 a3
17 - - D -- OUTPUT 0 1 0 0 a4
31 - - F -- TRI 0 1 0 9 d0
32 - - F -- TRI 0 1 0 9 d1
33 - - F -- TRI 0 1 0 9 d2
36 - - - 24 TRI 0 1 0 9 d3
37 - - - 23 TRI 0 1 0 9 d4
38 - - - 22 TRI 0 1 0 9 d5
39 - - - 21 TRI 0 1 0 9 d6
41 - - - 20 TRI 0 1 0 10 d7
20 - - D -- OUTPUT 0 1 0 0 in
135 - - - 19 OUTPUT 0 1 0 0 out
96 - - B -- OUTPUT 0 1 0 0 p1
100 - - A -- OUTPUT 0 1 0 0 r0
102 - - A -- OUTPUT 0 1 0 0 r1
64 - - - 09 OUTPUT 0 1 0 0 r2
63 - - - 10 OUTPUT 0 1 0 0 r3
95 - - B -- OUTPUT 0 1 0 0 r4
65 - - - 09 OUTPUT 0 1 0 0 r5
91 - - C -- OUTPUT 0 1 0 0 r6
121 - - - 10 OUTPUT 0 1 0 0 r7
42 - - - 19 OUTPUT 0 1 0 0 t1
99 - - B -- OUTPUT 0 1 0 0 t2
136 - - - 20 OUTPUT 0 1 0 0 t3
144 - - A -- OUTPUT 0 1 0 0 t4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\md\cpumodel.rpt
cpumodel
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 19 OR2 ! 0 3 1 5 |in_out:8|:35
- 4 - B 19 OR2 ! 0 3 1 2 |in_out:8|:38
- 6 - A 20 AND2 0 2 1 10 |kong_sim:100|jie:101|T4 (|kong_sim:100|jie:101|:15)
- 2 - A 19 AND2 0 3 1 0 |kong_sim:100|jie:101|T1 (|kong_sim:100|jie:101|:17)
- 3 - A 19 AND2 0 3 1 50 |kong_sim:100|jie:101|T2 (|kong_sim:100|jie:101|:19)
- 4 - A 20 AND2 0 2 1 6 |kong_sim:100|jie:101|T3 (|kong_sim:100|jie:101|:20)
- 5 - A 19 OR2 1 1 0 3 |kong_sim:100|jie:101|:33
- 1 - A 20 AND2 ! 1 0 0 2 |kong_sim:100|jie:101|:37
- 3 - A 20 OR2 ! 1 2 0 1 |kong_sim:100|jie:101|:38
- 4 - A 19 OR2 1 2 0 3 |kong_sim:100|jie:101|:52
- 1 - A 19 DFFE 1 1 0 2 |kong_sim:100|jie:101|7474:40|1Q (|kong_sim:100|jie:101|7474:40|:9)
- 2 - A 20 DFFE 0 4 0 5 |kong_sim:100|jie:101|7474:41|1Q (|kong_sim:100|jie:101|7474:41|:9)
- 8 - A 19 DFFE 0 2 0 4 |kong_sim:100|jie:101|74175:42|4Q (|kong_sim:100|jie:101|74175:42|:13)
- 7 - A 19 DFFE 0 3 0 3 |kong_sim:100|jie:101|74175:42|3Q (|kong_sim:100|jie:101|74175:42|:14)
- 6 - A 19 DFFE 0 3 0 3 |kong_sim:100|jie:101|74175:42|2Q (|kong_sim:100|jie:101|74175:42|:15)
- 3 - B 04 AND2 s 0 3 0 4 |kong_sim:100|rom:97|CPUROM:85|~95~1
- 2 - B 12 AND2 0 3 0 7 |kong_sim:100|rom:97|CPUROM:85|:95
- 6 - B 12 AND2 0 2 0 5 |kong_sim:100|rom:97|CPUROM:85|:101
- 6 - B 04 OR2 s 0 3 0 5 |kong_sim:100|rom:97|CPUROM:85|~107~1
- 7 - B 09 OR2 ! 0 3 0 10 |kong_sim:100|rom:97|CPUROM:85|:107
- 5 - B 12 AND2 0 2 0 8 |kong_sim:100|rom:97|CPUROM:85|:113
- 1 - B 09 OR2 ! 0 3 0 3 |kong_sim:100|rom:97|CPUROM:85|:119
- 6 - B 11 OR2 ! 0 2 0 4 |kong_sim:100|rom:97|CPUROM:85|:125
- 4 - B 09 AND2 0 3 0 6 |kong_sim:100|rom:97|CPUROM:85|:131
- 8 - B 04 AND2 s ! 0 3 0 6 |kong_sim:100|rom:97|CPUROM:85|~137~1
- 5 - B 05 OR2 ! 0 2 0 6 |kong_sim:100|rom:97|CPUROM:85|:137
- 3 - B 09 AND2 s 0 2 0 7 |kong_sim:100|rom:97|CPUROM:85|~161~1
- 1 - B 05 AND2 s ! 0 3 0 9 |kong_sim:100|rom:97|CPUROM:85|~179~1
- 3 - B 05 OR2 ! 0 2 0 3 |kong_sim:100|rom:97|CPUROM:85|:179
- 8 - B 05 AND2 s 0 3 0 5 |kong_sim:100|rom:97|CPUROM:85|~185~1
- 7 - B 05 OR2 ! 0 2 0 1 |kong_sim:100|rom:97|CPUROM:85|:185
- 2 - B 04 AND2 s 0 3 0 4 |kong_sim:100|rom:97|CPUROM:85|~191~1
- 2 - B 05 AND2 s 0 2 0 8 |kong_sim:100|rom:97|CPUROM:85|~191~2
- 2 - B 07 AND2 0 2 0 2 |kong_sim:100|rom:97|CPUROM:85|:191
- 5 - B 09 OR2 ! 0 3 0 1 |kong_sim:100|rom:97|CPUROM:85|:203
- 1 - B 12 OR2 ! 0 4 0 1 |kong_sim:100|rom:97|CPUROM:85|:437
- 8 - B 12 OR2 ! 0 4 0 2 |kong_sim:100|rom:97|CPUROM:85|:448
- 6 - B 05 OR2 0 4 0 2 |kong_sim:100|rom:97|CPUROM:85|:461
- 3 - B 07 OR2 0 3 0 1 |kong_sim:100|rom:97|CPUROM:85|:488
- 1 - B 07 AND2 s 0 3 0 1 |kong_sim:100|rom:97|CPUROM:85|~490~1
- 1 - B 11 AND2 s 0 2 0 5 |kong_sim:100|rom:97|CPUROM:85|~499~1
- 5 - B 07 OR2 0 4 0 2 |kong_sim:100|rom:97|CPUROM:85|:505
- 1 - B 02 OR2 s 0 3 0 2 |kong_sim:100|rom:97|CPUROM:85|~1168~1
- 5 - B 11 AND2 0 3 0 1 |kong_sim:100|rom:97|CPUROM:85|:1168
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