time.tan.qmsg

数字秒表的设计

{ "Info" "ITDB_TSU_RESULT" "cnt:inst1\|cqi\[0\] ena clk 1.862 ns register " "Info: tsu for register \"cnt:inst1\|cqi\[0\]\" (data pin = \"ena\", clock pin = \"clk\") is 1.862 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.216 ns + Longest pin register " "Info: + Longest pin to register delay is 9.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ena 1 PIN PIN_50 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_50; Fanout = 22; PIN Node = 'ena'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { ena } "NODE_NAME" } "" } } { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 320 0 168 336 "ena" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.880 ns) + CELL(0.867 ns) 9.216 ns cnt:inst1\|cqi\[0\] 2 REG LC_X13_Y10_N7 6 " "Info: 2: + IC(6.880 ns) + CELL(0.867 ns) = 9.216 ns; Loc. = LC_X13_Y10_N7; Fanout = 6; REG Node = 'cnt:inst1\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cy