time.tan.qmsg

数字秒表的设计

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 27 " "Warning: Circuit may not operate. Detected 27 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "cnt:inst6\|cqi\[0\] cnt:inst6\|cqi\[0\] clk 1.084 ns " "Info: Found hold time violation between source  pin or register \"cnt:inst6\|cqi\[0\]\" and destination pin or register \"cnt:inst6\|cqi\[0\]\" for clock \"clk\" (Hold time is 1.084 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.145 ns + Largest " "Info: + Largest clock skew is 2.145 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 40.645 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 40.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 45; CLK Node = 'clk'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { clk } "NODE_NAME" } "" } } { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 112 0 168 128 "clk" "" } { 72 536 568 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns clkgen:inst\|clk_scan 2 REG LC_X27_Y10_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N0; Fanout = 4; REG Node = 'clkgen:inst\|clk_scan'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.697 ns" { clk clkgen:inst|clk_scan } "NODE_NAME" } "" } } { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.514 ns) + CELL(0.935 ns) 7.615 ns cnt:inst1\|cqi\[0\] 3 REG LC_X13_Y10_N7 6 " "Info: 3: + IC(3.514 ns) + CELL(0.935 ns) = 7.615 ns; Loc. = LC_X13_Y10_N7; Fanout = 6; REG Node = 'cnt:inst1\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "4.449 ns" { clkgen:inst|clk_scan cnt:inst1|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.590 ns) 8.820 ns cnt:inst1\|reduce_nor~0 4 COMB LC_X13_Y10_N4 4 " "Info: 4: + IC(0.615 ns) + CELL(0.590 ns) = 8.820 ns; Loc. = LC_X13_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst1\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.205 ns" { cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.932 ns) + CELL(0.935 ns) 14.687 ns cnt:inst2\|cqi\[3\] 5 REG LC_X13_Y10_N9 6 " "Info: 5: + IC(4.932 ns) + CELL(0.935 ns) = 14.687 ns; Loc. = LC_X13_Y10_N9; Fanout = 6; REG Node = 'cnt:inst2\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.867 ns" { cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.590 ns) 15.857 ns cnt:inst2\|reduce_nor~0 6 COMB LC_X13_Y10_N5 4 " "Info: 6: + IC(0.580 ns) + CELL(0.590 ns) = 15.857 ns; Loc. = LC_X13_Y10_N5; Fanout = 4; COMB Node = 'cnt:inst2\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.170 ns" { cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.177 ns) + CELL(0.935 ns) 20.969 ns cnt:inst3\|cqi\[3\] 7 REG LC_X12_Y16_N9 6 " "Info: 7: + IC(4.177 ns) + CELL(0.935 ns) = 20.969 ns; Loc. = LC_X12_Y16_N9; Fanout = 6; REG Node = 'cnt:inst3\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.112 ns" { cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.442 ns) 22.198 ns cnt:inst3\|reduce_nor~0 8 COMB LC_X11_Y16_N5 3 " "Info: 8: + IC(0.787 ns) + CELL(0.442 ns) = 22.198 ns; Loc. = LC_X11_Y16_N5; Fanout = 3; COMB Node = 'cnt:inst3\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.229 ns" { cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.744 ns) + CELL(0.935 ns) 27.877 ns cnt:inst4\|cqi\[1\] 9 REG LC_X20_Y10_N5 5 " "Info: 9: + IC(4.744 ns) + CELL(0.935 ns) = 27.877 ns; Loc. = LC_X20_Y10_N5; Fanout = 5; REG Node = 'cnt:inst4\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.679 ns" { cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.442 ns) 28.859 ns cnt:inst4\|reduce_nor~0 10 COMB LC_X20_Y10_N4 4 " "Info: 10: + IC(0.540 ns) + CELL(0.442 ns) = 28.859 ns; Loc. = LC_X20_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst4\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.982 ns" { cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.211 ns) + CELL(0.935 ns) 34.005 ns cnt:inst5\|cqi\[3\] 11 REG LC_X12_Y16_N2 6 " "Info: 11: + IC(4.211 ns) + CELL(0.935 ns) = 34.005 ns; Loc. = LC_X12_Y16_N2; Fanout = 6; REG Node = 'cnt:inst5\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.146 ns" { cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.590 ns) 35.170 ns cnt:inst5\|reduce_nor~0 12 COMB LC_X12_Y16_N0 3 " "Info: 12: + IC(0.575 ns) + CELL(0.590 ns) = 35.170 ns; Loc. = LC_X12_Y16_N0; Fanout = 3; COMB Node = 'cnt:inst5\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.165 ns" { cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.764 ns) + CELL(0.711 ns) 40.645 ns cnt:inst6\|cqi\[0\] 13 REG LC_X11_Y16_N0 4 " "Info: 13: + IC(4.764 ns) + CELL(0.711 ns) = 40.645 ns; Loc. = LC_X11_Y16_N0; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.475 ns" { cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.444 ns 25.70 % " "Info: Total cell delay = 10.444 ns ( 25.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "30.201 ns 74.30 % " "Info: Total interconnect delay = 30.201 ns ( 74.30 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.615ns 4.932ns 0.58ns 4.177ns 0.787ns 4.744ns 0.54ns 4.211ns 0.575ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.935ns 0.59ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.59ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 38.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 38.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 45; CLK Node = 'clk'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { clk } "NODE_NAME" } "" } } { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 112 0 168 128 "clk" "" } { 72 536 568 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns clkgen:inst\|clk_scan 2 REG LC_X27_Y10_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N0; Fanout = 4; REG Node = 'clkgen:inst\|clk_scan'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.697 ns" { clk clkgen:inst|clk_scan } "NODE_NAME" } "" } } { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.514 ns) + CELL(0.935 ns) 7.615 ns cnt:inst1\|cqi\[3\] 3 REG LC_X13_Y10_N1 6 " "Info: 3: + IC(3.514 ns) + CELL(0.935 ns) = 7.615 ns; Loc. = LC_X13_Y10_N1; Fanout = 6; REG Node = 'cnt:inst1\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "4.449 ns" { clkgen:inst|clk_scan cnt:inst1|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.114 ns) 8.293 ns cnt:inst1\|reduce_nor~0 4 COMB LC_X13_Y10_N4 4 " "Info: 4: + IC(0.564 ns) + CELL(0.114 ns) = 8.293 ns; Loc. = LC_X13_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst1\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.678 ns" { cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.932 ns) + CELL(0.935 ns) 14.160 ns cnt:inst2\|cqi\[1\] 5 REG LC_X13_Y10_N6 6 " "Info: 5: + IC(4.932 ns) + CELL(0.935 ns) = 14.160 ns; Loc. = LC_X13_Y10_N6; Fanout = 6; REG Node = 'cnt:inst2\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.867 ns" { cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.114 ns) 14.858 ns cnt:inst2\|reduce_nor~0 6 COMB LC_X13_Y10_N5 4 " "Info: 6: + IC(0.584 ns) + CELL(0.114 ns) = 14.858 ns; Loc. = LC_X13_Y10_N5; Fanout = 4; COMB Node = 'cnt:inst2\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.698 ns" { cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.177 ns) + CELL(0.935 ns) 19.970 ns cnt:inst3\|cqi\[1\] 7 REG LC_X11_Y16_N2 6 " "Info: 7: + IC(4.177 ns) + CELL(0.935 ns) = 19.970 ns; Loc. = LC_X11_Y16_N2; Fanout = 6; REG Node = 'cnt:inst3\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.112 ns" { cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.292 ns) 20.829 ns cnt:inst3\|reduce_nor~0 8 COMB LC_X11_Y16_N5 3 " "Info: 8: + IC(0.567 ns) + CELL(0.292 ns) = 20.829 ns; Loc. = LC_X11_Y16_N5; Fanout = 3; COMB Node = 'cnt:inst3\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.859 ns" { cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.744 ns) + CELL(0.935 ns) 26.508 ns cnt:inst4\|cqi\[0\] 9 REG LC_X20_Y10_N6 5 " "Info: 9: + IC(4.744 ns) + CELL(0.935 ns) = 26.508 ns; Loc. = LC_X20_Y10_N6; Fanout = 5; REG Node = 'cnt:inst4\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.679 ns" { cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.114 ns) 27.183 ns cnt:inst4\|reduce_nor~0 10 COMB LC_X20_Y10_N4 4 " "Info: 10: + IC(0.561 ns) + CELL(0.114 ns) = 27.183 ns; Loc. = LC_X20_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst4\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.675 ns" { cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.211 ns) + CELL(0.935 ns) 32.329 ns cnt:inst5\|cqi\[1\] 11 REG LC_X12_Y16_N5 6 " "Info: 11: + IC(4.211 ns) + CELL(0.935 ns) = 32.329 ns; Loc. = LC_X12_Y16_N5; Fanout = 6; REG Node = 'cnt:inst5\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.146 ns" { cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.114 ns) 33.025 ns cnt:inst5\|reduce_nor~0 12 COMB LC_X12_Y16_N0 3 " "Info: 12: + IC(0.582 ns) + CELL(0.114 ns) = 33.025 ns; Loc. = LC_X12_Y16_N0; Fanout = 3; COMB Node = 'cnt:inst5\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.696 ns" { cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.764 ns) + CELL(0.711 ns) 38.500 ns cnt:inst6\|cqi\[0\] 13 REG LC_X11_Y16_N0 4 " "Info: 13: + IC(4.764 ns) + CELL(0.711 ns) = 38.500 ns; Loc. = LC_X11_Y16_N0; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.475 ns" { cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.538 ns 22.18 % " "Info: Total cell delay = 8.538 ns ( 22.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "29.962 ns 77.82 % " "Info: Total interconnect delay = 29.962 ns ( 77.82 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "38.500 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "38.500 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.564ns 4.932ns 0.584ns 4.177ns 0.567ns 4.744ns 0.561ns 4.211ns 0.582ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.292ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.615ns 4.932ns 0.58ns 4.177ns 0.787ns 4.744ns 0.54ns 4.211ns 0.575ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.935ns 0.59ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.59ns 0.711ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "38.500 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "38.500 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.564ns 4.932ns 0.584ns 4.177ns 0.567ns 4.744ns 0.561ns 4.211ns 0.582ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.292ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.852 ns - Shortest register register " "Info: - Shortest register to register delay is 0.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt:inst6\|cqi\[0\] 1 REG LC_X11_Y16_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N0; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.309 ns) 0.852 ns cnt:inst6\|cqi\[0\] 2 REG LC_X11_Y16_N0 4 " "Info: 2: + IC(0.543 ns) + CELL(0.309 ns) = 0.852 ns; Loc. = LC_X11_Y16_N0; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.852 ns" { cnt:inst6|cqi[0] cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 36.27 % " "Info: Total cell delay = 0.309 ns ( 36.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.543 ns 63.73 % " "Info: Total interconnect delay = 0.543 ns ( 63.73 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.852 ns" { cnt:inst6|cqi[0] cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.852 ns" { cnt:inst6|cqi[0] cnt:inst6|cqi[0] } { 0.0ns 0.543ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.615ns 4.932ns 0.58ns 4.177ns 0.787ns 4.744ns 0.54ns 4.211ns 0.575ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.935ns 0.59ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.59ns 0.711ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "38.500 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "38.500 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[3] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[1] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[1] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[0] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[1] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[0] } { 0.0ns 0.0ns 0.762ns 3.514ns 0.564ns 4.932ns 0.584ns 4.177ns 0.567ns 4.744ns 0.561ns 4.211ns 0.582ns 4.764ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.292ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.852 ns" { cnt:inst6|cqi[0] cnt:inst6|cqi[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.852 ns" { cnt:inst6|cqi[0] cnt:inst6|cqi[0] } { 0.0ns 0.543ns } { 0.0ns 0.309ns } } }  } 0}