📄 time.tan.qmsg

📁 数字秒表的设计
💻 QMSG
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "25 " "Warning: Found 25 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "cnt:inst4\|reduce_nor~0 " "Info: Detected gated clock \"cnt:inst4\|reduce_nor~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst4\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst5\|cqi\[2\] " "Info: Detected ripple clock \"cnt:inst5\|cqi\[2\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|cqi\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst5\|cqi\[1\] " "Info: Detected ripple clock \"cnt:inst5\|cqi\[1\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|cqi\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst5\|cqi\[3\] " "Info: Detected ripple clock \"cnt:inst5\|cqi\[3\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|cqi\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst5\|cqi\[0\] " "Info: Detected ripple clock \"cnt:inst5\|cqi\[0\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|cqi\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "cnt:inst3\|reduce_nor~0 " "Info: Detected gated clock \"cnt:inst3\|reduce_nor~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst4\|cqi\[1\] " "Info: Detected ripple clock \"cnt:inst4\|cqi\[1\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst4\|cqi\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst4\|cqi\[2\] " "Info: Detected ripple clock \"cnt:inst4\|cqi\[2\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst4\|cqi\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst4\|cqi\[0\] " "Info: Detected ripple clock \"cnt:inst4\|cqi\[0\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst4\|cqi\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "cnt:inst2\|reduce_nor~0 " "Info: Detected gated clock \"cnt:inst2\|reduce_nor~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst3\|cqi\[2\] " "Info: Detected ripple clock \"cnt:inst3\|cqi\[2\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|cqi\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst3\|cqi\[3\] " "Info: Detected ripple clock \"cnt:inst3\|cqi\[3\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|cqi\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst3\|cqi\[1\] " "Info: Detected ripple clock \"cnt:inst3\|cqi\[1\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|cqi\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst3\|cqi\[0\] " "Info: Detected ripple clock \"cnt:inst3\|cqi\[0\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|cqi\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "cnt:inst5\|reduce_nor~0 " "Info: Detected gated clock \"cnt:inst5\|reduce_nor~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clkgen:inst\|clk_scan " "Info: Detected ripple clock \"clkgen:inst\|clk_scan\" as buffer" {  } { { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkgen:inst\|clk_scan" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "cnt:inst1\|reduce_nor~0 " "Info: Detected gated clock \"cnt:inst1\|reduce_nor~0\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|reduce_nor~0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst1\|cqi\[3\] " "Info: Detected ripple clock \"cnt:inst1\|cqi\[3\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|cqi\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst2\|cqi\[3\] " "Info: Detected ripple clock \"cnt:inst2\|cqi\[3\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|cqi\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst1\|cqi\[2\] " "Info: Detected ripple clock \"cnt:inst1\|cqi\[2\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|cqi\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst2\|cqi\[2\] " "Info: Detected ripple clock \"cnt:inst2\|cqi\[2\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|cqi\[2\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst1\|cqi\[1\] " "Info: Detected ripple clock \"cnt:inst1\|cqi\[1\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|cqi\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst2\|cqi\[1\] " "Info: Detected ripple clock \"cnt:inst2\|cqi\[1\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|cqi\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst1\|cqi\[0\] " "Info: Detected ripple clock \"cnt:inst1\|cqi\[0\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|cqi\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cnt:inst2\|cqi\[0\] " "Info: Detected ripple clock \"cnt:inst2\|cqi\[0\]\" as buffer" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|cqi\[0\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt:inst6\|cqi\[1\] register xianshi:inst7\|dout\[1\] 24.32 MHz 41.123 ns Internal " "Info: Clock \"clk\" has Internal fmax of 24.32 MHz between source register \"cnt:inst6\|cqi\[1\]\" and destination register \"xianshi:inst7\|dout\[1\]\" (period= 41.123 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.171 ns + Longest register register " "Info: + Longest register to register delay is 3.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt:inst6\|cqi\[1\] 1 REG LC_X11_Y16_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N9; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.590 ns) 1.855 ns xianshi:inst7\|dout~629 2 COMB LC_X12_Y14_N2 1 " "Info: 2: + IC(1.265 ns) + CELL(0.590 ns) = 1.855 ns; Loc. = LC_X12_Y14_N2; Fanout = 1; COMB Node = 'xianshi:inst7\|dout~629'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.855 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.151 ns xianshi:inst7\|dout~630 3 COMB LC_X12_Y14_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.151 ns; Loc. = LC_X12_Y14_N3; Fanout = 1; COMB Node = 'xianshi:inst7\|dout~630'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.296 ns" { xianshi:inst7|dout~629 xianshi:inst7|dout~630 } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.607 ns) 3.171 ns xianshi:inst7\|dout\[1\] 4 REG LC_X12_Y14_N4 7 " "Info: 4: + IC(0.413 ns) + CELL(0.607 ns) = 3.171 ns; Loc. = LC_X12_Y14_N4; Fanout = 7; REG Node = 'xianshi:inst7\|dout\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.020 ns" { xianshi:inst7|dout~630 xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.311 ns 41.34 % " "Info: Total cell delay = 1.311 ns ( 41.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.860 ns 58.66 % " "Info: Total interconnect delay = 1.860 ns ( 58.66 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "3.171 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 xianshi:inst7|dout~630 xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.171 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 xianshi:inst7|dout~630 xianshi:inst7|dout[1] } { 0.000ns 1.265ns 0.182ns 0.413ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-37.691 ns - Smallest " "Info: - Smallest clock skew is -37.691 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 45; CLK Node = 'clk'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { clk } "NODE_NAME" } "" } } { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 112 0 168 128 "clk" "" } { 72 536 568 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns xianshi:inst7\|dout\[1\] 2 REG LC_X12_Y14_N4 7 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y14_N4; Fanout = 7; REG Node = 'xianshi:inst7\|dout\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.485 ns" { clk xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "2.954 ns" { clk xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 xianshi:inst7|dout[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 40.645 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 40.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 45; CLK Node = 'clk'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { clk } "NODE_NAME" } "" } } { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 112 0 168 128 "clk" "" } { 72 536 568 88 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns clkgen:inst\|clk_scan 2 REG LC_X27_Y10_N0 4 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N0; Fanout = 4; REG Node = 'clkgen:inst\|clk_scan'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.697 ns" { clk clkgen:inst|clk_scan } "NODE_NAME" } "" } } { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.514 ns) + CELL(0.935 ns) 7.615 ns cnt:inst1\|cqi\[0\] 3 REG LC_X13_Y10_N7 6 " "Info: 3: + IC(3.514 ns) + CELL(0.935 ns) = 7.615 ns; Loc. = LC_X13_Y10_N7; Fanout = 6; REG Node = 'cnt:inst1\|cqi\[0\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "4.449 ns" { clkgen:inst|clk_scan cnt:inst1|cqi[0] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.590 ns) 8.820 ns cnt:inst1\|reduce_nor~0 4 COMB LC_X13_Y10_N4 4 " "Info: 4: + IC(0.615 ns) + CELL(0.590 ns) = 8.820 ns; Loc. = LC_X13_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst1\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.205 ns" { cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.932 ns) + CELL(0.935 ns) 14.687 ns cnt:inst2\|cqi\[3\] 5 REG LC_X13_Y10_N9 6 " "Info: 5: + IC(4.932 ns) + CELL(0.935 ns) = 14.687 ns; Loc. = LC_X13_Y10_N9; Fanout = 6; REG Node = 'cnt:inst2\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.867 ns" { cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.590 ns) 15.857 ns cnt:inst2\|reduce_nor~0 6 COMB LC_X13_Y10_N5 4 " "Info: 6: + IC(0.580 ns) + CELL(0.590 ns) = 15.857 ns; Loc. = LC_X13_Y10_N5; Fanout = 4; COMB Node = 'cnt:inst2\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.170 ns" { cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.177 ns) + CELL(0.935 ns) 20.969 ns cnt:inst3\|cqi\[3\] 7 REG LC_X12_Y16_N9 6 " "Info: 7: + IC(4.177 ns) + CELL(0.935 ns) = 20.969 ns; Loc. = LC_X12_Y16_N9; Fanout = 6; REG Node = 'cnt:inst3\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.112 ns" { cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.442 ns) 22.198 ns cnt:inst3\|reduce_nor~0 8 COMB LC_X11_Y16_N5 3 " "Info: 8: + IC(0.787 ns) + CELL(0.442 ns) = 22.198 ns; Loc. = LC_X11_Y16_N5; Fanout = 3; COMB Node = 'cnt:inst3\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.229 ns" { cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.744 ns) + CELL(0.935 ns) 27.877 ns cnt:inst4\|cqi\[1\] 9 REG LC_X20_Y10_N5 5 " "Info: 9: + IC(4.744 ns) + CELL(0.935 ns) = 27.877 ns; Loc. = LC_X20_Y10_N5; Fanout = 5; REG Node = 'cnt:inst4\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.679 ns" { cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.442 ns) 28.859 ns cnt:inst4\|reduce_nor~0 10 COMB LC_X20_Y10_N4 4 " "Info: 10: + IC(0.540 ns) + CELL(0.442 ns) = 28.859 ns; Loc. = LC_X20_Y10_N4; Fanout = 4; COMB Node = 'cnt:inst4\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.982 ns" { cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.211 ns) + CELL(0.935 ns) 34.005 ns cnt:inst5\|cqi\[3\] 11 REG LC_X12_Y16_N2 6 " "Info: 11: + IC(4.211 ns) + CELL(0.935 ns) = 34.005 ns; Loc. = LC_X12_Y16_N2; Fanout = 6; REG Node = 'cnt:inst5\|cqi\[3\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.146 ns" { cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.575 ns) + CELL(0.590 ns) 35.170 ns cnt:inst5\|reduce_nor~0 12 COMB LC_X12_Y16_N0 3 " "Info: 12: + IC(0.575 ns) + CELL(0.590 ns) = 35.170 ns; Loc. = LC_X12_Y16_N0; Fanout = 3; COMB Node = 'cnt:inst5\|reduce_nor~0'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.165 ns" { cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.764 ns) + CELL(0.711 ns) 40.645 ns cnt:inst6\|cqi\[1\] 13 REG LC_X11_Y16_N9 4 " "Info: 13: + IC(4.764 ns) + CELL(0.711 ns) = 40.645 ns; Loc. = LC_X11_Y16_N9; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "5.475 ns" { cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.444 ns 25.70 % " "Info: Total cell delay = 10.444 ns ( 25.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "30.201 ns 74.30 % " "Info: Total interconnect delay = 30.201 ns ( 74.30 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } { 0.000ns 0.000ns 0.762ns 3.514ns 0.615ns 4.932ns 0.580ns 4.177ns 0.787ns 4.744ns 0.540ns 4.211ns 0.575ns 4.764ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.935ns 0.590ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.590ns 0.711ns } } }  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "2.954 ns" { clk xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 xianshi:inst7|dout[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } { 0.000ns 0.000ns 0.762ns 3.514ns 0.615ns 4.932ns 0.580ns 4.177ns 0.787ns 4.744ns 0.540ns 4.211ns 0.575ns 4.764ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.935ns 0.590ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.590ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "3.171 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 xianshi:inst7|dout~630 xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.171 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 xianshi:inst7|dout~630 xianshi:inst7|dout[1] } { 0.000ns 1.265ns 0.182ns 0.413ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "2.954 ns" { clk xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 xianshi:inst7|dout[1] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "40.645 ns" { clk clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "40.645 ns" { clk clk~out0 clkgen:inst|clk_scan cnt:inst1|cqi[0] cnt:inst1|reduce_nor~0 cnt:inst2|cqi[3] cnt:inst2|reduce_nor~0 cnt:inst3|cqi[3] cnt:inst3|reduce_nor~0 cnt:inst4|cqi[1] cnt:inst4|reduce_nor~0 cnt:inst5|cqi[3] cnt:inst5|reduce_nor~0 cnt:inst6|cqi[1] } { 0.000ns 0.000ns 0.762ns 3.514ns 0.615ns 4.932ns 0.580ns 4.177ns 0.787ns 4.744ns 0.540ns 4.211ns 0.575ns 4.764ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.935ns 0.590ns 0.935ns 0.442ns 0.935ns 0.442ns 0.935ns 0.590ns 0.711ns } } }  } 0}
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