time.map.rpt

来自「数字秒表的设计」· RPT 代码 · 共 316 行 · 第 1/2 页

; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |time                      ; 153 (0)     ; 67           ; 0           ; 13   ; 0            ; 86 (0)       ; 11 (0)            ; 56 (0)           ; 37 (0)          ; |time               ;
;    |clkgen:inst|           ; 49 (49)     ; 20           ; 0           ; 0    ; 0            ; 29 (29)      ; 11 (11)           ; 9 (9)            ; 19 (19)         ; |time|clkgen:inst   ;
;    |cnt:inst1|             ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |time|cnt:inst1     ;
;    |cnt:inst2|             ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |time|cnt:inst2     ;
;    |cnt:inst3|             ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |time|cnt:inst3     ;
;    |cnt:inst4|             ; 4 (4)       ; 3            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 3 (3)            ; 0 (0)           ; |time|cnt:inst4     ;
;    |cnt:inst5|             ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |time|cnt:inst5     ;
;    |cnt:inst6|             ; 3 (3)       ; 3            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 3 (3)            ; 0 (0)           ; |time|cnt:inst6     ;
;    |decoder:inst8|         ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |time|decoder:inst8 ;
;    |xianshi:inst7|         ; 70 (70)     ; 25           ; 0           ; 0    ; 0            ; 45 (45)      ; 0 (0)             ; 25 (25)          ; 18 (18)         ; |time|xianshi:inst7 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 67    ;
; Number of registers using Synchronous Clear  ; 18    ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 29    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 7:1                ; 18 bits   ; 72 LEs        ; 18 LEs               ; 54 LEs                 ; Yes        ; |time|xianshi:inst7|qq[9]   ;
; 7:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |time|xianshi:inst7|dout[0] ;
; 7:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |time|xianshi:inst7|w1[0]   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 10    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: clkgen:inst ;
+----------------+--------+--------------------------------+
; Parameter Name ; Value  ; Type                           ;
+----------------+--------+--------------------------------+
; fpl            ; 500000 ; Untyped                        ;
+----------------+--------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst2 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 10    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst3 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 10    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst4 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 6     ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst5 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 10    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: cnt:inst6 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; n              ; 6     ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/cyclone/fpga/成功完成/数字秒表的设计/time.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Jun 23 16:29:36 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off time -c time
Info: Found 2 design units, including 1 entities, in source file cnt.vhd
    Info: Found design unit 1: cnt-art
    Info: Found entity 1: cnt
Info: Found 2 design units, including 1 entities, in source file clkgen.vhd
    Info: Found design unit 1: clkgen-behavioral
    Info: Found entity 1: clkgen
Info: Found 1 design units, including 1 entities, in source file time.bdf
    Info: Found entity 1: time
Info: Found 2 design units, including 1 entities, in source file xianshi.vhd
    Info: Found design unit 1: xianshi-behav
    Info: Found entity 1: xianshi
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
    Info: Found design unit 1: decoder-Behavioral
    Info: Found entity 1: decoder
Info: Elaborating entity "time" for the top level hierarchy
Info: Elaborating entity "decoder" for hierarchy "decoder:inst8"
Info: Elaborating entity "xianshi" for hierarchy "xianshi:inst7"
Info: Elaborating entity "cnt" for hierarchy "cnt:inst1"
Info: Elaborating entity "clkgen" for hierarchy "clkgen:inst"
Info: Elaborating entity "cnt" for hierarchy "cnt:inst4"
Warning: Reduced register "cnt:inst6|cqi[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "cnt:inst4|cqi[3]" with stuck data_in port to stuck value GND
Info: Implemented 166 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 10 output pins
    Info: Implemented 153 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Jun 23 16:29:42 2008
    Info: Elapsed time: 00:00:06