📄 time.map.rpt
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Analysis & Synthesis report for time
Mon Jun 23 16:29:42 2008
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Multiplexer Restructuring Statistics (Restructuring Performed)
9. Parameter Settings for User Entity Instance: cnt:inst1
10. Parameter Settings for User Entity Instance: clkgen:inst
11. Parameter Settings for User Entity Instance: cnt:inst2
12. Parameter Settings for User Entity Instance: cnt:inst3
13. Parameter Settings for User Entity Instance: cnt:inst4
14. Parameter Settings for User Entity Instance: cnt:inst5
15. Parameter Settings for User Entity Instance: cnt:inst6
16. Analysis & Synthesis Equations
17. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jun 23 16:29:42 2008 ;
; Quartus II Version ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name ; time ;
; Top-level Entity Name ; time ;
; Family ; Cyclone ;
; Total logic elements ; 153 ;
; Total pins ; 13 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP1C6Q240C8 ; ;
; Top-level entity name ; time ; time ;
; Family name ; Cyclone ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
; cnt.vhd ; yes ; User VHDL File ; D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd ;
; clkgen.vhd ; yes ; User VHDL File ; D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd ;
; time.bdf ; yes ; User Block Diagram/Schematic File ; D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf ;
; xianshi.vhd ; yes ; User VHDL File ; D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd ;
; decoder.vhd ; yes ; User VHDL File ; D:/cyclone/fpga/成功完成/数字秒表的设计/decoder.vhd ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Total logic elements ; 153 ;
; Total combinational functions ; 142 ;
; -- Total 4-input functions ; 75 ;
; -- Total 3-input functions ; 22 ;
; -- Total 2-input functions ; 8 ;
; -- Total 1-input functions ; 37 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 67 ;
; Total logic cells in carry chains ; 37 ;
; I/O pins ; 13 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 45 ;
; Total fan-out ; 619 ;
; Average fan-out ; 3.73 ;
+-----------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
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